1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ X11 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun#include "rk3288-fennec.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Rockchip RK3288 Fennec Board"; 12*4882a593Smuzhiyun compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun chosen { 15*4882a593Smuzhiyun stdout-path = &uart2; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun}; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun&dmc { 20*4882a593Smuzhiyun rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d 21*4882a593Smuzhiyun 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 22*4882a593Smuzhiyun 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 23*4882a593Smuzhiyun 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 24*4882a593Smuzhiyun 0x8 0x1f4>; 25*4882a593Smuzhiyun rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 26*4882a593Smuzhiyun 0x0 0xc3 0x6 0x2>; 27*4882a593Smuzhiyun rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun&pinctrl { 31*4882a593Smuzhiyun u-boot,dm-pre-reloc; 32*4882a593Smuzhiyun}; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun&pwm1 { 35*4882a593Smuzhiyun status = "okay"; 36*4882a593Smuzhiyun}; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun&uart2 { 39*4882a593Smuzhiyun u-boot,dm-pre-reloc; 40*4882a593Smuzhiyun reg-shift = <2>; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun&sdmmc { 44*4882a593Smuzhiyun u-boot,dm-pre-reloc; 45*4882a593Smuzhiyun}; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun&emmc { 48*4882a593Smuzhiyun u-boot,dm-pre-reloc; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&gpio3 { 52*4882a593Smuzhiyun u-boot,dm-pre-reloc; 53*4882a593Smuzhiyun}; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun&gpio8 { 56*4882a593Smuzhiyun u-boot,dm-pre-reloc; 57*4882a593Smuzhiyun}; 58