xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/r8a7795-salvator-x.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Device Tree Source for the Salvator-X board
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Corp.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License
7*4882a593Smuzhiyun * version 2.  This program is licensed "as is" without any warranty of any
8*4882a593Smuzhiyun * kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/*
12*4882a593Smuzhiyun * SSI-AK4613
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * This command is required when Playback/Capture
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun *	amixer set "DVC Out" 100%
17*4882a593Smuzhiyun *	amixer set "DVC In" 100%
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * You can use Mute
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun *	amixer set "DVC Out Mute" on
22*4882a593Smuzhiyun *	amixer set "DVC In Mute" on
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * You can use Volume Ramp
25*4882a593Smuzhiyun *
26*4882a593Smuzhiyun *	amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
27*4882a593Smuzhiyun *	amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
28*4882a593Smuzhiyun *	amixer set "DVC Out Ramp" on
29*4882a593Smuzhiyun *	aplay xxx.wav &
30*4882a593Smuzhiyun *	amixer set "DVC Out"  80%  // Volume Down
31*4882a593Smuzhiyun *	amixer set "DVC Out" 100%  // Volume Up
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun/dts-v1/;
35*4882a593Smuzhiyun#include "r8a7795.dtsi"
36*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun/ {
39*4882a593Smuzhiyun	model = "Renesas Salvator-X board based on r8a7795";
40*4882a593Smuzhiyun	compatible = "renesas,salvator-x", "renesas,r8a7795";
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	aliases {
43*4882a593Smuzhiyun		serial0 = &scif2;
44*4882a593Smuzhiyun		serial1 = &scif1;
45*4882a593Smuzhiyun		ethernet0 = &avb;
46*4882a593Smuzhiyun	};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun	chosen {
49*4882a593Smuzhiyun		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
50*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	memory@48000000 {
54*4882a593Smuzhiyun		device_type = "memory";
55*4882a593Smuzhiyun		/* first 128MB is reserved for secure area. */
56*4882a593Smuzhiyun		reg = <0x0 0x48000000 0x0 0x38000000>;
57*4882a593Smuzhiyun	};
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun	x12_clk: x12 {
60*4882a593Smuzhiyun		compatible = "fixed-clock";
61*4882a593Smuzhiyun		#clock-cells = <0>;
62*4882a593Smuzhiyun		clock-frequency = <24576000>;
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	reg_1p8v: regulator0 {
66*4882a593Smuzhiyun		compatible = "regulator-fixed";
67*4882a593Smuzhiyun		regulator-name = "fixed-1.8V";
68*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
69*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
70*4882a593Smuzhiyun		regulator-boot-on;
71*4882a593Smuzhiyun		regulator-always-on;
72*4882a593Smuzhiyun	};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun	reg_3p3v: regulator1 {
75*4882a593Smuzhiyun		compatible = "regulator-fixed";
76*4882a593Smuzhiyun		regulator-name = "fixed-3.3V";
77*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
78*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
79*4882a593Smuzhiyun		regulator-boot-on;
80*4882a593Smuzhiyun		regulator-always-on;
81*4882a593Smuzhiyun	};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun	vcc_sdhi0: regulator-vcc-sdhi0 {
84*4882a593Smuzhiyun		compatible = "regulator-fixed";
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun		regulator-name = "SDHI0 Vcc";
87*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
88*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
91*4882a593Smuzhiyun		enable-active-high;
92*4882a593Smuzhiyun	};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun	vccq_sdhi0: regulator-vccq-sdhi0 {
95*4882a593Smuzhiyun		compatible = "regulator-gpio";
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun		regulator-name = "SDHI0 VccQ";
98*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
99*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
102*4882a593Smuzhiyun		gpios-states = <1>;
103*4882a593Smuzhiyun		states = <3300000 1
104*4882a593Smuzhiyun			  1800000 0>;
105*4882a593Smuzhiyun	};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun	vcc_sdhi3: regulator-vcc-sdhi3 {
108*4882a593Smuzhiyun		compatible = "regulator-fixed";
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun		regulator-name = "SDHI3 Vcc";
111*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
112*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun		gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
115*4882a593Smuzhiyun		enable-active-high;
116*4882a593Smuzhiyun	};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun	vccq_sdhi3: regulator-vccq-sdhi3 {
119*4882a593Smuzhiyun		compatible = "regulator-gpio";
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun		regulator-name = "SDHI3 VccQ";
122*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
123*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun		gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
126*4882a593Smuzhiyun		gpios-states = <1>;
127*4882a593Smuzhiyun		states = <3300000 1
128*4882a593Smuzhiyun			  1800000 0>;
129*4882a593Smuzhiyun	};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun	vbus0_usb2: regulator-vbus0-usb2 {
132*4882a593Smuzhiyun		compatible = "regulator-fixed";
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun		regulator-name = "USB20_VBUS0";
135*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
136*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun		gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
139*4882a593Smuzhiyun		enable-active-high;
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun	audio_clkout: audio_clkout {
143*4882a593Smuzhiyun		/*
144*4882a593Smuzhiyun		 * This is same as <&rcar_sound 0>
145*4882a593Smuzhiyun		 * but needed to avoid cs2000/rcar_sound probe dead-lock
146*4882a593Smuzhiyun		 */
147*4882a593Smuzhiyun		compatible = "fixed-clock";
148*4882a593Smuzhiyun		#clock-cells = <0>;
149*4882a593Smuzhiyun		clock-frequency = <11289600>;
150*4882a593Smuzhiyun	};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun	rsnd_ak4613: sound {
153*4882a593Smuzhiyun		compatible = "simple-audio-card";
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun		simple-audio-card,format = "left_j";
156*4882a593Smuzhiyun		simple-audio-card,bitclock-master = <&sndcpu>;
157*4882a593Smuzhiyun		simple-audio-card,frame-master = <&sndcpu>;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun		sndcpu: simple-audio-card,cpu {
160*4882a593Smuzhiyun			sound-dai = <&rcar_sound>;
161*4882a593Smuzhiyun		};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun		sndcodec: simple-audio-card,codec {
164*4882a593Smuzhiyun			sound-dai = <&ak4613>;
165*4882a593Smuzhiyun		};
166*4882a593Smuzhiyun	};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun	vga-encoder {
169*4882a593Smuzhiyun		compatible = "adi,adv7123";
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun		ports {
172*4882a593Smuzhiyun			#address-cells = <1>;
173*4882a593Smuzhiyun			#size-cells = <0>;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun			port@0 {
176*4882a593Smuzhiyun				reg = <0>;
177*4882a593Smuzhiyun				adv7123_in: endpoint {
178*4882a593Smuzhiyun					remote-endpoint = <&du_out_rgb>;
179*4882a593Smuzhiyun				};
180*4882a593Smuzhiyun			};
181*4882a593Smuzhiyun			port@1 {
182*4882a593Smuzhiyun				reg = <1>;
183*4882a593Smuzhiyun				adv7123_out: endpoint {
184*4882a593Smuzhiyun					remote-endpoint = <&vga_in>;
185*4882a593Smuzhiyun				};
186*4882a593Smuzhiyun			};
187*4882a593Smuzhiyun		};
188*4882a593Smuzhiyun	};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun	vga {
191*4882a593Smuzhiyun		compatible = "vga-connector";
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun		port {
194*4882a593Smuzhiyun			vga_in: endpoint {
195*4882a593Smuzhiyun				remote-endpoint = <&adv7123_out>;
196*4882a593Smuzhiyun			};
197*4882a593Smuzhiyun		};
198*4882a593Smuzhiyun	};
199*4882a593Smuzhiyun};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun&du {
202*4882a593Smuzhiyun	pinctrl-0 = <&du_pins>;
203*4882a593Smuzhiyun	pinctrl-names = "default";
204*4882a593Smuzhiyun	status = "okay";
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun	ports {
207*4882a593Smuzhiyun		port@0 {
208*4882a593Smuzhiyun			endpoint {
209*4882a593Smuzhiyun				remote-endpoint = <&adv7123_in>;
210*4882a593Smuzhiyun			};
211*4882a593Smuzhiyun		};
212*4882a593Smuzhiyun		port@3 {
213*4882a593Smuzhiyun			lvds_connector: endpoint {
214*4882a593Smuzhiyun			};
215*4882a593Smuzhiyun		};
216*4882a593Smuzhiyun	};
217*4882a593Smuzhiyun};
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun&extal_clk {
220*4882a593Smuzhiyun	clock-frequency = <16666666>;
221*4882a593Smuzhiyun};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun&extalr_clk {
224*4882a593Smuzhiyun	clock-frequency = <32768>;
225*4882a593Smuzhiyun};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun&pfc {
228*4882a593Smuzhiyun	pinctrl-0 = <&scif_clk_pins>;
229*4882a593Smuzhiyun	pinctrl-names = "default";
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun	scif1_pins: scif1 {
232*4882a593Smuzhiyun		groups = "scif1_data_a", "scif1_ctrl";
233*4882a593Smuzhiyun		function = "scif1";
234*4882a593Smuzhiyun	};
235*4882a593Smuzhiyun	scif2_pins: scif2 {
236*4882a593Smuzhiyun		groups = "scif2_data_a";
237*4882a593Smuzhiyun		function = "scif2";
238*4882a593Smuzhiyun	};
239*4882a593Smuzhiyun	scif_clk_pins: scif_clk {
240*4882a593Smuzhiyun		groups = "scif_clk_a";
241*4882a593Smuzhiyun		function = "scif_clk";
242*4882a593Smuzhiyun	};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun	i2c2_pins: i2c2 {
245*4882a593Smuzhiyun		groups = "i2c2_a";
246*4882a593Smuzhiyun		function = "i2c2";
247*4882a593Smuzhiyun	};
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun	avb_pins: avb {
250*4882a593Smuzhiyun		mux {
251*4882a593Smuzhiyun			groups = "avb_link", "avb_phy_int", "avb_mdc",
252*4882a593Smuzhiyun				 "avb_mii";
253*4882a593Smuzhiyun			function = "avb";
254*4882a593Smuzhiyun		};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun		pins_mdc {
257*4882a593Smuzhiyun			groups = "avb_mdc";
258*4882a593Smuzhiyun			drive-strength = <24>;
259*4882a593Smuzhiyun		};
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun		pins_mii_tx {
262*4882a593Smuzhiyun			pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
263*4882a593Smuzhiyun			       "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
264*4882a593Smuzhiyun			drive-strength = <12>;
265*4882a593Smuzhiyun		};
266*4882a593Smuzhiyun	};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun	du_pins: du {
269*4882a593Smuzhiyun		groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
270*4882a593Smuzhiyun		function = "du";
271*4882a593Smuzhiyun	};
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun	sdhi0_pins: sd0 {
274*4882a593Smuzhiyun		groups = "sdhi0_data4", "sdhi0_ctrl";
275*4882a593Smuzhiyun		function = "sdhi0";
276*4882a593Smuzhiyun		power-source = <3300>;
277*4882a593Smuzhiyun	};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun	sdhi0_pins_uhs: sd0_uhs {
280*4882a593Smuzhiyun		groups = "sdhi0_data4", "sdhi0_ctrl";
281*4882a593Smuzhiyun		function = "sdhi0";
282*4882a593Smuzhiyun		power-source = <1800>;
283*4882a593Smuzhiyun	};
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun	sdhi2_pins: sd2 {
286*4882a593Smuzhiyun		groups = "sdhi2_data8", "sdhi2_ctrl";
287*4882a593Smuzhiyun		function = "sdhi2";
288*4882a593Smuzhiyun		power-source = <3300>;
289*4882a593Smuzhiyun	};
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun	sdhi2_pins_uhs: sd2_uhs {
292*4882a593Smuzhiyun		groups = "sdhi2_data8", "sdhi2_ctrl";
293*4882a593Smuzhiyun		function = "sdhi2";
294*4882a593Smuzhiyun		power-source = <1800>;
295*4882a593Smuzhiyun	};
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun	sdhi3_pins: sd3 {
298*4882a593Smuzhiyun		groups = "sdhi3_data4", "sdhi3_ctrl";
299*4882a593Smuzhiyun		function = "sdhi3";
300*4882a593Smuzhiyun		power-source = <3300>;
301*4882a593Smuzhiyun	};
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun	sdhi3_pins_uhs: sd3_uhs {
304*4882a593Smuzhiyun		groups = "sdhi3_data4", "sdhi3_ctrl";
305*4882a593Smuzhiyun		function = "sdhi3";
306*4882a593Smuzhiyun		power-source = <1800>;
307*4882a593Smuzhiyun	};
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun	sound_pins: sound {
310*4882a593Smuzhiyun		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
311*4882a593Smuzhiyun		function = "ssi";
312*4882a593Smuzhiyun	};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun	sound_clk_pins: sound_clk {
315*4882a593Smuzhiyun		groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
316*4882a593Smuzhiyun			 "audio_clkout_a", "audio_clkout3_a";
317*4882a593Smuzhiyun		function = "audio_clk";
318*4882a593Smuzhiyun	};
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun	usb0_pins: usb0 {
321*4882a593Smuzhiyun		groups = "usb0";
322*4882a593Smuzhiyun		function = "usb0";
323*4882a593Smuzhiyun	};
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun	usb1_pins: usb1 {
326*4882a593Smuzhiyun		mux {
327*4882a593Smuzhiyun			groups = "usb1";
328*4882a593Smuzhiyun			function = "usb1";
329*4882a593Smuzhiyun		};
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun		ovc {
332*4882a593Smuzhiyun			pins = "GP_6_27";
333*4882a593Smuzhiyun			bias-pull-up;
334*4882a593Smuzhiyun		};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun		pwen {
337*4882a593Smuzhiyun			pins = "GP_6_26";
338*4882a593Smuzhiyun			bias-pull-down;
339*4882a593Smuzhiyun		};
340*4882a593Smuzhiyun	};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun	usb2_pins: usb2 {
343*4882a593Smuzhiyun		groups = "usb2";
344*4882a593Smuzhiyun		function = "usb2";
345*4882a593Smuzhiyun	};
346*4882a593Smuzhiyun};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun&scif1 {
349*4882a593Smuzhiyun	pinctrl-0 = <&scif1_pins>;
350*4882a593Smuzhiyun	pinctrl-names = "default";
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun	uart-has-rtscts;
353*4882a593Smuzhiyun	status = "okay";
354*4882a593Smuzhiyun};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun&scif2 {
357*4882a593Smuzhiyun	pinctrl-0 = <&scif2_pins>;
358*4882a593Smuzhiyun	pinctrl-names = "default";
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun	status = "okay";
361*4882a593Smuzhiyun};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun&scif_clk {
364*4882a593Smuzhiyun	clock-frequency = <14745600>;
365*4882a593Smuzhiyun};
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun&i2c2 {
368*4882a593Smuzhiyun	pinctrl-0 = <&i2c2_pins>;
369*4882a593Smuzhiyun	pinctrl-names = "default";
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun	status = "okay";
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun	clock-frequency = <100000>;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun	ak4613: codec@10 {
376*4882a593Smuzhiyun		compatible = "asahi-kasei,ak4613";
377*4882a593Smuzhiyun		#sound-dai-cells = <0>;
378*4882a593Smuzhiyun		reg = <0x10>;
379*4882a593Smuzhiyun		clocks = <&rcar_sound 3>;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun		asahi-kasei,in1-single-end;
382*4882a593Smuzhiyun		asahi-kasei,in2-single-end;
383*4882a593Smuzhiyun		asahi-kasei,out1-single-end;
384*4882a593Smuzhiyun		asahi-kasei,out2-single-end;
385*4882a593Smuzhiyun		asahi-kasei,out3-single-end;
386*4882a593Smuzhiyun		asahi-kasei,out4-single-end;
387*4882a593Smuzhiyun		asahi-kasei,out5-single-end;
388*4882a593Smuzhiyun		asahi-kasei,out6-single-end;
389*4882a593Smuzhiyun	};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun	cs2000: clk_multiplier@4f {
392*4882a593Smuzhiyun		#clock-cells = <0>;
393*4882a593Smuzhiyun		compatible = "cirrus,cs2000-cp";
394*4882a593Smuzhiyun		reg = <0x4f>;
395*4882a593Smuzhiyun		clocks = <&audio_clkout>, <&x12_clk>;
396*4882a593Smuzhiyun		clock-names = "clk_in", "ref_clk";
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun		assigned-clocks = <&cs2000>;
399*4882a593Smuzhiyun		assigned-clock-rates = <24576000>; /* 1/1 divide */
400*4882a593Smuzhiyun	};
401*4882a593Smuzhiyun};
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun&rcar_sound {
404*4882a593Smuzhiyun	pinctrl-0 = <&sound_pins &sound_clk_pins>;
405*4882a593Smuzhiyun	pinctrl-names = "default";
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun	/* Single DAI */
408*4882a593Smuzhiyun	#sound-dai-cells = <0>;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun	/* audio_clkout0/1/2/3 */
411*4882a593Smuzhiyun	#clock-cells = <1>;
412*4882a593Smuzhiyun	clock-frequency = <11289600>;
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun	status = "okay";
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun	/* update <audio_clk_b> to <cs2000> */
417*4882a593Smuzhiyun	clocks = <&cpg CPG_MOD 1005>,
418*4882a593Smuzhiyun		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
419*4882a593Smuzhiyun		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
420*4882a593Smuzhiyun		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
421*4882a593Smuzhiyun		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
422*4882a593Smuzhiyun		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
423*4882a593Smuzhiyun		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
424*4882a593Smuzhiyun		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
425*4882a593Smuzhiyun		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
426*4882a593Smuzhiyun		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
427*4882a593Smuzhiyun		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
428*4882a593Smuzhiyun		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
429*4882a593Smuzhiyun		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
430*4882a593Smuzhiyun		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
431*4882a593Smuzhiyun		 <&audio_clk_a>, <&cs2000>,
432*4882a593Smuzhiyun		 <&audio_clk_c>,
433*4882a593Smuzhiyun		 <&cpg CPG_CORE R8A7795_CLK_S0D4>;
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun	rcar_sound,dai {
436*4882a593Smuzhiyun		dai0 {
437*4882a593Smuzhiyun			playback = <&ssi0 &src0 &dvc0>;
438*4882a593Smuzhiyun			capture  = <&ssi1 &src1 &dvc1>;
439*4882a593Smuzhiyun		};
440*4882a593Smuzhiyun	};
441*4882a593Smuzhiyun};
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun&sata {
444*4882a593Smuzhiyun	status = "okay";
445*4882a593Smuzhiyun};
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun&sdhi0 {
448*4882a593Smuzhiyun	pinctrl-0 = <&sdhi0_pins>;
449*4882a593Smuzhiyun	pinctrl-1 = <&sdhi0_pins_uhs>;
450*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun	vmmc-supply = <&vcc_sdhi0>;
453*4882a593Smuzhiyun	vqmmc-supply = <&vccq_sdhi0>;
454*4882a593Smuzhiyun	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
455*4882a593Smuzhiyun	wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
456*4882a593Smuzhiyun	bus-width = <4>;
457*4882a593Smuzhiyun	sd-uhs-sdr50;
458*4882a593Smuzhiyun	status = "okay";
459*4882a593Smuzhiyun};
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun&sdhi2 {
462*4882a593Smuzhiyun	/* used for on-board 8bit eMMC */
463*4882a593Smuzhiyun	pinctrl-0 = <&sdhi2_pins>;
464*4882a593Smuzhiyun	pinctrl-1 = <&sdhi2_pins_uhs>;
465*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
468*4882a593Smuzhiyun	vqmmc-supply = <&reg_1p8v>;
469*4882a593Smuzhiyun	bus-width = <8>;
470*4882a593Smuzhiyun	non-removable;
471*4882a593Smuzhiyun	status = "okay";
472*4882a593Smuzhiyun};
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun&sdhi3 {
475*4882a593Smuzhiyun	pinctrl-0 = <&sdhi3_pins>;
476*4882a593Smuzhiyun	pinctrl-1 = <&sdhi3_pins_uhs>;
477*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun	vmmc-supply = <&vcc_sdhi3>;
480*4882a593Smuzhiyun	vqmmc-supply = <&vccq_sdhi3>;
481*4882a593Smuzhiyun	cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
482*4882a593Smuzhiyun	wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
483*4882a593Smuzhiyun	bus-width = <4>;
484*4882a593Smuzhiyun	sd-uhs-sdr50;
485*4882a593Smuzhiyun	status = "okay";
486*4882a593Smuzhiyun};
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun&ssi1 {
489*4882a593Smuzhiyun	shared-pin;
490*4882a593Smuzhiyun};
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun&wdt0 {
493*4882a593Smuzhiyun	timeout-sec = <60>;
494*4882a593Smuzhiyun	status = "okay";
495*4882a593Smuzhiyun};
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun&audio_clk_a {
498*4882a593Smuzhiyun	clock-frequency = <22579200>;
499*4882a593Smuzhiyun};
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun&i2c_dvfs {
502*4882a593Smuzhiyun	status = "okay";
503*4882a593Smuzhiyun};
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun&avb {
506*4882a593Smuzhiyun	pinctrl-0 = <&avb_pins>;
507*4882a593Smuzhiyun	pinctrl-names = "default";
508*4882a593Smuzhiyun	renesas,no-ether-link;
509*4882a593Smuzhiyun	phy-handle = <&phy0>;
510*4882a593Smuzhiyun	status = "okay";
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun	phy0: ethernet-phy@0 {
513*4882a593Smuzhiyun		rxc-skew-ps = <1500>;
514*4882a593Smuzhiyun		reg = <0>;
515*4882a593Smuzhiyun		interrupt-parent = <&gpio2>;
516*4882a593Smuzhiyun		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
517*4882a593Smuzhiyun	};
518*4882a593Smuzhiyun};
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun&xhci0 {
521*4882a593Smuzhiyun	status = "okay";
522*4882a593Smuzhiyun};
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun&usb2_phy0 {
525*4882a593Smuzhiyun	pinctrl-0 = <&usb0_pins>;
526*4882a593Smuzhiyun	pinctrl-names = "default";
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun	vbus-supply = <&vbus0_usb2>;
529*4882a593Smuzhiyun	status = "okay";
530*4882a593Smuzhiyun};
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun&usb2_phy1 {
533*4882a593Smuzhiyun	pinctrl-0 = <&usb1_pins>;
534*4882a593Smuzhiyun	pinctrl-names = "default";
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun	status = "okay";
537*4882a593Smuzhiyun};
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun&usb2_phy2 {
540*4882a593Smuzhiyun	pinctrl-0 = <&usb2_pins>;
541*4882a593Smuzhiyun	pinctrl-names = "default";
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun	status = "okay";
544*4882a593Smuzhiyun};
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun&ehci0 {
547*4882a593Smuzhiyun	status = "okay";
548*4882a593Smuzhiyun};
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun&ehci1 {
551*4882a593Smuzhiyun	status = "okay";
552*4882a593Smuzhiyun};
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun&ehci2 {
555*4882a593Smuzhiyun	status = "okay";
556*4882a593Smuzhiyun};
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun&ohci0 {
559*4882a593Smuzhiyun	status = "okay";
560*4882a593Smuzhiyun};
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun&ohci1 {
563*4882a593Smuzhiyun	status = "okay";
564*4882a593Smuzhiyun};
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun&ohci2 {
567*4882a593Smuzhiyun	status = "okay";
568*4882a593Smuzhiyun};
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun&hsusb {
571*4882a593Smuzhiyun	status = "okay";
572*4882a593Smuzhiyun};
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun&pcie_bus_clk {
575*4882a593Smuzhiyun	clock-frequency = <100000000>;
576*4882a593Smuzhiyun};
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun&pciec0 {
579*4882a593Smuzhiyun	status = "okay";
580*4882a593Smuzhiyun};
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun&pciec1 {
583*4882a593Smuzhiyun	status = "okay";
584*4882a593Smuzhiyun};
585