xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/omap36xx.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Device Tree Source for OMAP3 SoC
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License
7*4882a593Smuzhiyun * version 2.  This program is licensed "as is" without any warranty of any
8*4882a593Smuzhiyun * kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun#include <dt-bindings/media/omap3-isp.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun#include "omap3.dtsi"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun/ {
16*4882a593Smuzhiyun       aliases {
17*4882a593Smuzhiyun               serial3 = &uart4;
18*4882a593Smuzhiyun       };
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun       cpus {
21*4882a593Smuzhiyun               /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
22*4882a593Smuzhiyun               cpu@0 {
23*4882a593Smuzhiyun                       operating-points = <
24*4882a593Smuzhiyun                               /* kHz    uV */
25*4882a593Smuzhiyun                               300000  1012500
26*4882a593Smuzhiyun                               600000  1200000
27*4882a593Smuzhiyun                               800000  1325000
28*4882a593Smuzhiyun                       >;
29*4882a593Smuzhiyun                       clock-latency = <300000>; /* From legacy driver */
30*4882a593Smuzhiyun               };
31*4882a593Smuzhiyun       };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun       ocp@68000000 {
34*4882a593Smuzhiyun               uart4: serial@49042000 {
35*4882a593Smuzhiyun                       compatible = "ti,omap3-uart";
36*4882a593Smuzhiyun                       reg = <0x49042000 0x400>;
37*4882a593Smuzhiyun                       interrupts = <80>;
38*4882a593Smuzhiyun                       dmas = <&sdma 81 &sdma 82>;
39*4882a593Smuzhiyun                       dma-names = "tx", "rx";
40*4882a593Smuzhiyun                       ti,hwmods = "uart4";
41*4882a593Smuzhiyun                       clock-frequency = <48000000>;
42*4882a593Smuzhiyun               };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun               abb_mpu_iva: regulator-abb-mpu {
45*4882a593Smuzhiyun                       compatible = "ti,abb-v1";
46*4882a593Smuzhiyun                       regulator-name = "abb_mpu_iva";
47*4882a593Smuzhiyun                       #address-cells = <0>;
48*4882a593Smuzhiyun                       #size-cells = <0>;
49*4882a593Smuzhiyun                       reg = <0x483072f0 0x8>, <0x48306818 0x4>;
50*4882a593Smuzhiyun                       reg-names = "base-address", "int-address";
51*4882a593Smuzhiyun                       ti,tranxdone-status-mask = <0x4000000>;
52*4882a593Smuzhiyun                       clocks = <&sys_ck>;
53*4882a593Smuzhiyun                       ti,settling-time = <30>;
54*4882a593Smuzhiyun                       ti,clock-cycles = <8>;
55*4882a593Smuzhiyun                       ti,abb_info = <
56*4882a593Smuzhiyun                       /*uV            ABB     efuse   rbb_m   fbb_m   vset_m*/
57*4882a593Smuzhiyun                       1012500         0       0       0       0       0
58*4882a593Smuzhiyun                       1200000         0       0       0       0       0
59*4882a593Smuzhiyun                       1325000         0       0       0       0       0
60*4882a593Smuzhiyun                       1375000         1       0       0       0       0
61*4882a593Smuzhiyun                       >;
62*4882a593Smuzhiyun               };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun               omap3_pmx_core2: pinmux@480025a0 {
65*4882a593Smuzhiyun                       compatible = "ti,omap3-padconf", "pinctrl-single";
66*4882a593Smuzhiyun                       reg = <0x480025a0 0x5c>;
67*4882a593Smuzhiyun                       #address-cells = <1>;
68*4882a593Smuzhiyun                       #size-cells = <0>;
69*4882a593Smuzhiyun                       #interrupt-cells = <1>;
70*4882a593Smuzhiyun                       interrupt-controller;
71*4882a593Smuzhiyun                       pinctrl-single,register-width = <16>;
72*4882a593Smuzhiyun                       pinctrl-single,function-mask = <0xff1f>;
73*4882a593Smuzhiyun               };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun               isp: isp@480bc000 {
76*4882a593Smuzhiyun                       compatible = "ti,omap3-isp";
77*4882a593Smuzhiyun                       reg = <0x480bc000 0x12fc
78*4882a593Smuzhiyun                              0x480bd800 0x0600>;
79*4882a593Smuzhiyun                       interrupts = <24>;
80*4882a593Smuzhiyun                       iommus = <&mmu_isp>;
81*4882a593Smuzhiyun                       syscon = <&scm_conf 0x2f0>;
82*4882a593Smuzhiyun                       ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
83*4882a593Smuzhiyun                       #clock-cells = <1>;
84*4882a593Smuzhiyun                       ports {
85*4882a593Smuzhiyun                               #address-cells = <1>;
86*4882a593Smuzhiyun                               #size-cells = <0>;
87*4882a593Smuzhiyun                       };
88*4882a593Smuzhiyun               };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun               bandgap@48002524 {
91*4882a593Smuzhiyun                       reg = <0x48002524 0x4>;
92*4882a593Smuzhiyun                       compatible = "ti,omap36xx-bandgap";
93*4882a593Smuzhiyun                       #thermal-sensor-cells = <0>;
94*4882a593Smuzhiyun               };
95*4882a593Smuzhiyun       };
96*4882a593Smuzhiyun};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun/* OMAP3630 needs dss_96m_fck for VENC */
99*4882a593Smuzhiyun&venc {
100*4882a593Smuzhiyun       clocks = <&dss_tv_fck>, <&dss_96m_fck>;
101*4882a593Smuzhiyun       clock-names = "fck", "tv_dac_clk";
102*4882a593Smuzhiyun};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun&ssi {
105*4882a593Smuzhiyun       status = "ok";
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun       clocks = <&ssi_ssr_fck>,
108*4882a593Smuzhiyun                <&ssi_sst_fck>,
109*4882a593Smuzhiyun                <&ssi_ick>;
110*4882a593Smuzhiyun       clock-names = "ssi_ssr_fck",
111*4882a593Smuzhiyun                     "ssi_sst_fck",
112*4882a593Smuzhiyun                     "ssi_ick";
113*4882a593Smuzhiyun};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun/include/ "omap34xx-omap36xx-clocks.dtsi"
116*4882a593Smuzhiyun/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
117*4882a593Smuzhiyun/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
118*4882a593Smuzhiyun/include/ "omap36xx-clocks.dtsi"
119