1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Freescale ls1021a TWR board common device tree source 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2013-2015 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "ls1021a.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "LS1021A TWR Board"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun aliases { 15*4882a593Smuzhiyun enet2_rgmii_phy = &rgmii_phy1; 16*4882a593Smuzhiyun enet0_sgmii_phy = &sgmii_phy2; 17*4882a593Smuzhiyun enet1_sgmii_phy = &sgmii_phy0; 18*4882a593Smuzhiyun spi0 = &qspi; 19*4882a593Smuzhiyun spi1 = &dspi1; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun chosen { 23*4882a593Smuzhiyun stdout-path = &uart0; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun&qspi { 28*4882a593Smuzhiyun bus-num = <0>; 29*4882a593Smuzhiyun status = "okay"; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun qflash0: n25q128a13@0 { 32*4882a593Smuzhiyun #address-cells = <1>; 33*4882a593Smuzhiyun #size-cells = <1>; 34*4882a593Smuzhiyun compatible = "spi-flash"; 35*4882a593Smuzhiyun spi-max-frequency = <20000000>; 36*4882a593Smuzhiyun reg = <0>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun&dspi1 { 41*4882a593Smuzhiyun bus-num = <0>; 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun dspiflash: at26df081a@0 { 45*4882a593Smuzhiyun #address-cells = <1>; 46*4882a593Smuzhiyun #size-cells = <1>; 47*4882a593Smuzhiyun compatible = "spi-flash"; 48*4882a593Smuzhiyun spi-max-frequency = <16000000>; 49*4882a593Smuzhiyun spi-cpol; 50*4882a593Smuzhiyun spi-cpha; 51*4882a593Smuzhiyun reg = <0>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun}; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun&i2c0 { 56*4882a593Smuzhiyun status = "okay"; 57*4882a593Smuzhiyun}; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun&i2c1 { 60*4882a593Smuzhiyun status = "okay"; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun&ifc { 64*4882a593Smuzhiyun #address-cells = <2>; 65*4882a593Smuzhiyun #size-cells = <1>; 66*4882a593Smuzhiyun /* NOR Flash on board */ 67*4882a593Smuzhiyun ranges = <0x0 0x0 0x60000000 0x08000000>; 68*4882a593Smuzhiyun status = "okay"; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun nor@0,0 { 71*4882a593Smuzhiyun #address-cells = <1>; 72*4882a593Smuzhiyun #size-cells = <1>; 73*4882a593Smuzhiyun compatible = "cfi-flash"; 74*4882a593Smuzhiyun reg = <0x0 0x0 0x8000000>; 75*4882a593Smuzhiyun bank-width = <2>; 76*4882a593Smuzhiyun device-width = <1>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun&lpuart0 { 81*4882a593Smuzhiyun status = "okay"; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun&mdio0 { 85*4882a593Smuzhiyun sgmii_phy0: ethernet-phy@0 { 86*4882a593Smuzhiyun reg = <0x0>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun rgmii_phy1: ethernet-phy@1 { 89*4882a593Smuzhiyun reg = <0x1>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun sgmii_phy2: ethernet-phy@2 { 92*4882a593Smuzhiyun reg = <0x2>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun tbi1: tbi-phy@1f { 95*4882a593Smuzhiyun reg = <0x1f>; 96*4882a593Smuzhiyun device_type = "tbi-phy"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&uart0 { 101*4882a593Smuzhiyun status = "okay"; 102*4882a593Smuzhiyun}; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun&uart1 { 105*4882a593Smuzhiyun status = "okay"; 106*4882a593Smuzhiyun}; 107