xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/logicpd-som-lv.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
3*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as
4*4882a593Smuzhiyun * published by the Free Software Foundation.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	cpus {
11*4882a593Smuzhiyun		cpu@0 {
12*4882a593Smuzhiyun			cpu0-supply = <&vcc>;
13*4882a593Smuzhiyun		};
14*4882a593Smuzhiyun	};
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	memory@80000000 {
17*4882a593Smuzhiyun		device_type = "memory";
18*4882a593Smuzhiyun		reg = <0x80000000 0>;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	wl12xx_vmmc: wl12xx_vmmc {
22*4882a593Smuzhiyun		compatible = "regulator-fixed";
23*4882a593Smuzhiyun		regulator-name = "vwl1271";
24*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
25*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
26*4882a593Smuzhiyun		gpio = <&gpio1 3 0>;   /* gpio_3 */
27*4882a593Smuzhiyun		startup-delay-us = <70000>;
28*4882a593Smuzhiyun		enable-active-high;
29*4882a593Smuzhiyun		vin-supply = <&vmmc2>;
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	/* HS USB Host PHY on PORT 1 */
33*4882a593Smuzhiyun	hsusb2_phy: hsusb2_phy {
34*4882a593Smuzhiyun		compatible = "usb-nop-xceiv";
35*4882a593Smuzhiyun		reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
36*4882a593Smuzhiyun	};
37*4882a593Smuzhiyun};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun&gpmc {
40*4882a593Smuzhiyun	ranges = <0 0 0x00000000 0x1000000>;	/* CS0: 16MB for NAND */
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	nand@0,0 {
43*4882a593Smuzhiyun		compatible = "ti,omap2-nand";
44*4882a593Smuzhiyun		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
45*4882a593Smuzhiyun		interrupt-parent = <&gpmc>;
46*4882a593Smuzhiyun		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
47*4882a593Smuzhiyun			     <1 IRQ_TYPE_NONE>;	/* termcount */
48*4882a593Smuzhiyun		linux,mtd-name = "micron,mt29f4g16abbda3w";
49*4882a593Smuzhiyun		nand-bus-width = <16>;
50*4882a593Smuzhiyun		ti,nand-ecc-opt = "bch8";
51*4882a593Smuzhiyun		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
52*4882a593Smuzhiyun		gpmc,sync-clk-ps = <0>;
53*4882a593Smuzhiyun		gpmc,cs-on-ns = <0>;
54*4882a593Smuzhiyun		gpmc,cs-rd-off-ns = <44>;
55*4882a593Smuzhiyun		gpmc,cs-wr-off-ns = <44>;
56*4882a593Smuzhiyun		gpmc,adv-on-ns = <6>;
57*4882a593Smuzhiyun		gpmc,adv-rd-off-ns = <34>;
58*4882a593Smuzhiyun		gpmc,adv-wr-off-ns = <44>;
59*4882a593Smuzhiyun		gpmc,we-off-ns = <40>;
60*4882a593Smuzhiyun		gpmc,oe-off-ns = <54>;
61*4882a593Smuzhiyun		gpmc,access-ns = <64>;
62*4882a593Smuzhiyun		gpmc,rd-cycle-ns = <82>;
63*4882a593Smuzhiyun		gpmc,wr-cycle-ns = <82>;
64*4882a593Smuzhiyun		gpmc,wr-access-ns = <40>;
65*4882a593Smuzhiyun		gpmc,wr-data-mux-bus-ns = <0>;
66*4882a593Smuzhiyun		gpmc,device-width = <2>;
67*4882a593Smuzhiyun		#address-cells = <1>;
68*4882a593Smuzhiyun		#size-cells = <1>;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun		/* u-boot uses mtdparts=omap2-nand.0:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs) */
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun		x-loader@0 {
73*4882a593Smuzhiyun			label = "x-loader";
74*4882a593Smuzhiyun			reg = <0 0x80000>;
75*4882a593Smuzhiyun		};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun		bootloaders@80000 {
78*4882a593Smuzhiyun			label = "u-boot";
79*4882a593Smuzhiyun			reg = <0x80000 0x1e0000>;
80*4882a593Smuzhiyun		};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun		bootloaders_env@260000 {
83*4882a593Smuzhiyun			label = "u-boot-env";
84*4882a593Smuzhiyun			reg = <0x260000 0x20000>;
85*4882a593Smuzhiyun		};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun		kernel@280000 {
88*4882a593Smuzhiyun			label = "kernel";
89*4882a593Smuzhiyun			reg = <0x280000 0x400000>;
90*4882a593Smuzhiyun		};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun		filesystem@680000 {
93*4882a593Smuzhiyun			label = "fs";
94*4882a593Smuzhiyun			reg = <0x680000 0>;	/* 0 = MTDPART_SIZ_FULL */
95*4882a593Smuzhiyun		};
96*4882a593Smuzhiyun	};
97*4882a593Smuzhiyun};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun&i2c1 {
100*4882a593Smuzhiyun	clock-frequency = <400000>;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun	twl: twl@48 {
103*4882a593Smuzhiyun		reg = <0x48>;
104*4882a593Smuzhiyun		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
105*4882a593Smuzhiyun		interrupt-parent = <&intc>;
106*4882a593Smuzhiyun		twl_audio: audio {
107*4882a593Smuzhiyun			compatible = "ti,twl4030-audio";
108*4882a593Smuzhiyun			codec {
109*4882a593Smuzhiyun			};
110*4882a593Smuzhiyun		};
111*4882a593Smuzhiyun	};
112*4882a593Smuzhiyun};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun&i2c2 {
115*4882a593Smuzhiyun	clock-frequency = <400000>;
116*4882a593Smuzhiyun};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun&i2c3 {
119*4882a593Smuzhiyun	clock-frequency = <400000>;
120*4882a593Smuzhiyun};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun&mmc3 {
123*4882a593Smuzhiyun	interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
124*4882a593Smuzhiyun	pinctrl-0 = <&mmc3_pins>;
125*4882a593Smuzhiyun	pinctrl-names = "default";
126*4882a593Smuzhiyun	vmmc-supply = <&wl12xx_vmmc>;
127*4882a593Smuzhiyun	non-removable;
128*4882a593Smuzhiyun	bus-width = <4>;
129*4882a593Smuzhiyun	cap-power-off-card;
130*4882a593Smuzhiyun	#address-cells = <1>;
131*4882a593Smuzhiyun	#size-cells = <0>;
132*4882a593Smuzhiyun	wlcore: wlcore@2 {
133*4882a593Smuzhiyun		compatible = "ti,wl1273";
134*4882a593Smuzhiyun		reg = <2>;
135*4882a593Smuzhiyun		interrupt-parent = <&gpio5>;
136*4882a593Smuzhiyun		interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */
137*4882a593Smuzhiyun		ref-clock-frequency = <26000000>;
138*4882a593Smuzhiyun	};
139*4882a593Smuzhiyun};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun&usbhshost {
142*4882a593Smuzhiyun	port2-mode = "ehci-phy";
143*4882a593Smuzhiyun};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun&usbhsehci {
146*4882a593Smuzhiyun	phys = <0 &hsusb2_phy>;
147*4882a593Smuzhiyun};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun&omap3_pmx_core {
151*4882a593Smuzhiyun	pinctrl-names = "default";
152*4882a593Smuzhiyun	pinctrl-0 = <&hsusb2_pins>;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun	mmc3_pins: pinmux_mm3_pins {
155*4882a593Smuzhiyun		pinctrl-single,pins = <
156*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3)	/* sdmmc2_dat4.sdmmc3_dat0 */
157*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3)	/* sdmmc2_dat5.sdmmc3_dat1 */
158*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3)	/* sdmmc2_dat6.sdmmc3_dat2 */
159*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3)	/* sdmmc2_dat6.sdmmc3_dat3 */
160*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4)	/* mcbsp4_clkx.gpio_152 */
161*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4)	/* sys_boot1.gpio_3 */
162*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
163*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3)	/* mcspi1_cs2.sdmmc_clk */
164*4882a593Smuzhiyun		>;
165*4882a593Smuzhiyun	};
166*4882a593Smuzhiyun	mcbsp2_pins: pinmux_mcbsp2_pins {
167*4882a593Smuzhiyun		pinctrl-single,pins = <
168*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx */
169*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)        /* mcbsp2_clkx */
170*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)        /* mcbsp2_dr */
171*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)       /* mcbsp2_dx */
172*4882a593Smuzhiyun		>;
173*4882a593Smuzhiyun	};
174*4882a593Smuzhiyun	uart2_pins: pinmux_uart2_pins {
175*4882a593Smuzhiyun		pinctrl-single,pins = <
176*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0)	/* uart2_cts.uart2_cts */
177*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)	/* uart2_rts .uart2_rts*/
178*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)	/* uart2_tx.uart2_tx */
179*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)	/* uart2_rx.uart2_rx */
180*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)	/* GPIO_162,BT_EN */
181*4882a593Smuzhiyun		>;
182*4882a593Smuzhiyun	};
183*4882a593Smuzhiyun	mcspi1_pins: pinmux_mcspi1_pins {
184*4882a593Smuzhiyun		pinctrl-single,pins = <
185*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk.mcspi1_clk */
186*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_simo.mcspi1_simo */
187*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
188*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_cs0.mcspi1_cs0 */
189*4882a593Smuzhiyun		>;
190*4882a593Smuzhiyun	};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun	hsusb2_pins: pinmux_hsusb2_pins {
193*4882a593Smuzhiyun		pinctrl-single,pins = <
194*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi1_cs3.hsusb2_data2 */
195*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_clk.hsusb2_data7 */
196*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_simo.hsusb2_data4 */
197*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_somi.hsusb2_data5 */
198*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs0.hsusb2_data6 */
199*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs1.hsusb2_data3 */
200*4882a593Smuzhiyun		>;
201*4882a593Smuzhiyun	};
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun	hsusb_otg_pins: pinmux_hsusb_otg_pins {
204*4882a593Smuzhiyun		pinctrl-single,pins = <
205*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)	/* hsusb0_clk.hsusb0_clk */
206*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)	/* hsusb0_stp.hsusb0_stp */
207*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0)	/* hsusb0_dir.hsusb0_dir */
208*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0)	/* hsusb0_nxt.hsusb0_nxt */
209*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0)	/* hsusb0_data0.hsusb0_data0 */
210*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0)	/* hsusb0_data1.hsusb0_data1 */
211*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0)	/* hsusb0_data2.hsusb0_data2 */
212*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0)	/* hsusb0_data3.hsusb0_data3 */
213*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0)	/* hsusb0_data4.hsusb0_data4 */
214*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0)	/* hsusb0_data5.hsusb0_data5 */
215*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)	/* hsusb0_data6.hsusb0_data6 */
216*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)	/* hsusb0_data7.hsusb0_data7 */
217*4882a593Smuzhiyun		>;
218*4882a593Smuzhiyun	};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun&omap3_pmx_wkup {
224*4882a593Smuzhiyun	pinctrl-names = "default";
225*4882a593Smuzhiyun	pinctrl-0 = <&hsusb2_reset_pin>;
226*4882a593Smuzhiyun	hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
227*4882a593Smuzhiyun		pinctrl-single,pins = <
228*4882a593Smuzhiyun			OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4)	/* sys_boot2.gpio_4 */
229*4882a593Smuzhiyun		>;
230*4882a593Smuzhiyun	};
231*4882a593Smuzhiyun};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun&omap3_pmx_core2 {
234*4882a593Smuzhiyun	pinctrl-names = "default";
235*4882a593Smuzhiyun	pinctrl-0 = <&hsusb2_2_pins>;
236*4882a593Smuzhiyun	hsusb2_2_pins: pinmux_hsusb2_2_pins {
237*4882a593Smuzhiyun		pinctrl-single,pins = <
238*4882a593Smuzhiyun			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
239*4882a593Smuzhiyun			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
240*4882a593Smuzhiyun			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
241*4882a593Smuzhiyun			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
242*4882a593Smuzhiyun			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
243*4882a593Smuzhiyun			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
244*4882a593Smuzhiyun		>;
245*4882a593Smuzhiyun	};
246*4882a593Smuzhiyun};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun&uart2 {
249*4882a593Smuzhiyun	interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
250*4882a593Smuzhiyun	pinctrl-names = "default";
251*4882a593Smuzhiyun	pinctrl-0 = <&uart2_pins>;
252*4882a593Smuzhiyun};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun&mcspi1 {
255*4882a593Smuzhiyun	pinctrl-names = "default";
256*4882a593Smuzhiyun	pinctrl-0 = <&mcspi1_pins>;
257*4882a593Smuzhiyun};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun#include "twl4030.dtsi"
260*4882a593Smuzhiyun#include "twl4030_omap3.dtsi"
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun&twl {
263*4882a593Smuzhiyun	twl_power: power {
264*4882a593Smuzhiyun		compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
265*4882a593Smuzhiyun		ti,use_poweroff;
266*4882a593Smuzhiyun	};
267*4882a593Smuzhiyun};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun&twl_gpio {
270*4882a593Smuzhiyun	ti,use-leds;
271*4882a593Smuzhiyun};
272