1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright 2013-2014 Texas Instruments, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Keystone 2 lamarr SoC clock nodes 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 7*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 8*4882a593Smuzhiyun * published by the Free Software Foundation. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyunclocks { 12*4882a593Smuzhiyun armpllclk: armpllclk@2620370 { 13*4882a593Smuzhiyun #clock-cells = <0>; 14*4882a593Smuzhiyun compatible = "ti,keystone,pll-clock"; 15*4882a593Smuzhiyun clocks = <&refclksys>; 16*4882a593Smuzhiyun clock-output-names = "arm-pll-clk"; 17*4882a593Smuzhiyun reg = <0x02620370 4>; 18*4882a593Smuzhiyun reg-names = "control"; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun mainpllclk: mainpllclk@2310110 { 22*4882a593Smuzhiyun #clock-cells = <0>; 23*4882a593Smuzhiyun compatible = "ti,keystone,main-pll-clock"; 24*4882a593Smuzhiyun clocks = <&refclksys>; 25*4882a593Smuzhiyun reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; 26*4882a593Smuzhiyun reg-names = "control", "multiplier", "post-divider"; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun papllclk: papllclk@2620358 { 30*4882a593Smuzhiyun #clock-cells = <0>; 31*4882a593Smuzhiyun compatible = "ti,keystone,pll-clock"; 32*4882a593Smuzhiyun clocks = <&refclksys>; 33*4882a593Smuzhiyun clock-output-names = "papllclk"; 34*4882a593Smuzhiyun reg = <0x02620358 4>; 35*4882a593Smuzhiyun reg-names = "control"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun ddr3apllclk: ddr3apllclk@2620360 { 39*4882a593Smuzhiyun #clock-cells = <0>; 40*4882a593Smuzhiyun compatible = "ti,keystone,pll-clock"; 41*4882a593Smuzhiyun clocks = <&refclksys>; 42*4882a593Smuzhiyun clock-output-names = "ddr-3a-pll-clk"; 43*4882a593Smuzhiyun reg = <0x02620360 4>; 44*4882a593Smuzhiyun reg-names = "control"; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun clkdfeiqnsys: clkdfeiqnsys { 48*4882a593Smuzhiyun #clock-cells = <0>; 49*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 50*4882a593Smuzhiyun clocks = <&chipclk12>; 51*4882a593Smuzhiyun clock-output-names = "dfe"; 52*4882a593Smuzhiyun reg-names = "control", "domain"; 53*4882a593Smuzhiyun reg = <0x02350004 0xb00>, <0x02350000 0x400>; 54*4882a593Smuzhiyun domain-id = <0>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun clkpcie1: clkpcie1 { 58*4882a593Smuzhiyun #clock-cells = <0>; 59*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 60*4882a593Smuzhiyun clocks = <&chipclk12>; 61*4882a593Smuzhiyun clock-output-names = "pcie"; 62*4882a593Smuzhiyun reg = <0x0235002c 0xb00>, <0x02350000 0x400>; 63*4882a593Smuzhiyun reg-names = "control", "domain"; 64*4882a593Smuzhiyun domain-id = <4>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun clkgem1: clkgem1 { 68*4882a593Smuzhiyun #clock-cells = <0>; 69*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 70*4882a593Smuzhiyun clocks = <&chipclk1>; 71*4882a593Smuzhiyun clock-output-names = "gem1"; 72*4882a593Smuzhiyun reg = <0x02350040 0xb00>, <0x02350024 0x400>; 73*4882a593Smuzhiyun reg-names = "control", "domain"; 74*4882a593Smuzhiyun domain-id = <9>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun clkgem2: clkgem2 { 78*4882a593Smuzhiyun #clock-cells = <0>; 79*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 80*4882a593Smuzhiyun clocks = <&chipclk1>; 81*4882a593Smuzhiyun clock-output-names = "gem2"; 82*4882a593Smuzhiyun reg = <0x02350044 0xb00>, <0x02350028 0x400>; 83*4882a593Smuzhiyun reg-names = "control", "domain"; 84*4882a593Smuzhiyun domain-id = <10>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun clkgem3: clkgem3 { 88*4882a593Smuzhiyun #clock-cells = <0>; 89*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 90*4882a593Smuzhiyun clocks = <&chipclk1>; 91*4882a593Smuzhiyun clock-output-names = "gem3"; 92*4882a593Smuzhiyun reg = <0x02350048 0xb00>, <0x0235002c 0x400>; 93*4882a593Smuzhiyun reg-names = "control", "domain"; 94*4882a593Smuzhiyun domain-id = <11>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun clktac: clktac { 98*4882a593Smuzhiyun #clock-cells = <0>; 99*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 100*4882a593Smuzhiyun clocks = <&chipclk13>; 101*4882a593Smuzhiyun clock-output-names = "tac"; 102*4882a593Smuzhiyun reg = <0x02350064 0xb00>, <0x02350044 0x400>; 103*4882a593Smuzhiyun reg-names = "control", "domain"; 104*4882a593Smuzhiyun domain-id = <17>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun clkrac: clkrac { 108*4882a593Smuzhiyun #clock-cells = <0>; 109*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 110*4882a593Smuzhiyun clocks = <&chipclk13>; 111*4882a593Smuzhiyun clock-output-names = "rac"; 112*4882a593Smuzhiyun reg = <0x02350068 0xb00>, <0x02350044 0x400>; 113*4882a593Smuzhiyun reg-names = "control", "domain"; 114*4882a593Smuzhiyun domain-id = <17>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun clkdfepd0: clkdfepd0 { 118*4882a593Smuzhiyun #clock-cells = <0>; 119*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 120*4882a593Smuzhiyun clocks = <&chipclk13>; 121*4882a593Smuzhiyun clock-output-names = "dfe-pd0"; 122*4882a593Smuzhiyun reg = <0x0235006c 0xb00>, <0x02350044 0x400>; 123*4882a593Smuzhiyun reg-names = "control", "domain"; 124*4882a593Smuzhiyun domain-id = <18>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun clkfftc0: clkfftc0 { 128*4882a593Smuzhiyun #clock-cells = <0>; 129*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 130*4882a593Smuzhiyun clocks = <&chipclk13>; 131*4882a593Smuzhiyun clock-output-names = "fftc-0"; 132*4882a593Smuzhiyun reg = <0x02350070 0xb00>, <0x0235004c 0x400>; 133*4882a593Smuzhiyun reg-names = "control", "domain"; 134*4882a593Smuzhiyun domain-id = <19>; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun clkosr: clkosr { 138*4882a593Smuzhiyun #clock-cells = <0>; 139*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 140*4882a593Smuzhiyun clocks = <&chipclk13>; 141*4882a593Smuzhiyun clock-output-names = "osr"; 142*4882a593Smuzhiyun reg = <0x02350088 0xb00>, <0x0235004c 0x400>; 143*4882a593Smuzhiyun reg-names = "control", "domain"; 144*4882a593Smuzhiyun domain-id = <21>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun clktcp3d0: clktcp3d0 { 148*4882a593Smuzhiyun #clock-cells = <0>; 149*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 150*4882a593Smuzhiyun clocks = <&chipclk13>; 151*4882a593Smuzhiyun clock-output-names = "tcp3d-0"; 152*4882a593Smuzhiyun reg = <0x0235008c 0xb00>, <0x02350058 0x400>; 153*4882a593Smuzhiyun reg-names = "control", "domain"; 154*4882a593Smuzhiyun domain-id = <22>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun clktcp3d1: clktcp3d1 { 158*4882a593Smuzhiyun #clock-cells = <0>; 159*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 160*4882a593Smuzhiyun clocks = <&chipclk13>; 161*4882a593Smuzhiyun clock-output-names = "tcp3d-1"; 162*4882a593Smuzhiyun reg = <0x02350094 0xb00>, <0x02350058 0x400>; 163*4882a593Smuzhiyun reg-names = "control", "domain"; 164*4882a593Smuzhiyun domain-id = <23>; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun clkvcp0: clkvcp0 { 168*4882a593Smuzhiyun #clock-cells = <0>; 169*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 170*4882a593Smuzhiyun clocks = <&chipclk13>; 171*4882a593Smuzhiyun clock-output-names = "vcp-0"; 172*4882a593Smuzhiyun reg = <0x0235009c 0xb00>, <0x02350060 0x400>; 173*4882a593Smuzhiyun reg-names = "control", "domain"; 174*4882a593Smuzhiyun domain-id = <24>; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun clkvcp1: clkvcp1 { 178*4882a593Smuzhiyun #clock-cells = <0>; 179*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 180*4882a593Smuzhiyun clocks = <&chipclk13>; 181*4882a593Smuzhiyun clock-output-names = "vcp-1"; 182*4882a593Smuzhiyun reg = <0x023500a0 0xb00>, <0x02350060 0x400>; 183*4882a593Smuzhiyun reg-names = "control", "domain"; 184*4882a593Smuzhiyun domain-id = <24>; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun clkvcp2: clkvcp2 { 188*4882a593Smuzhiyun #clock-cells = <0>; 189*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 190*4882a593Smuzhiyun clocks = <&chipclk13>; 191*4882a593Smuzhiyun clock-output-names = "vcp-2"; 192*4882a593Smuzhiyun reg = <0x023500a4 0xb00>, <0x02350060 0x400>; 193*4882a593Smuzhiyun reg-names = "control", "domain"; 194*4882a593Smuzhiyun domain-id = <24>; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun clkvcp3: clkvcp3 { 198*4882a593Smuzhiyun #clock-cells = <0>; 199*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 200*4882a593Smuzhiyun clocks = <&chipclk13>; 201*4882a593Smuzhiyun clock-output-names = "vcp-3"; 202*4882a593Smuzhiyun reg = <0x023500a8 0xb00>, <0x02350060 0x400>; 203*4882a593Smuzhiyun reg-names = "control", "domain"; 204*4882a593Smuzhiyun domain-id = <24>; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun clkbcp: clkbcp { 208*4882a593Smuzhiyun #clock-cells = <0>; 209*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 210*4882a593Smuzhiyun clocks = <&chipclk13>; 211*4882a593Smuzhiyun clock-output-names = "bcp"; 212*4882a593Smuzhiyun reg = <0x023500bc 0xb00>, <0x02350068 0x400>; 213*4882a593Smuzhiyun reg-names = "control", "domain"; 214*4882a593Smuzhiyun domain-id = <26>; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun clkdfepd1: clkdfepd1 { 218*4882a593Smuzhiyun #clock-cells = <0>; 219*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 220*4882a593Smuzhiyun clocks = <&chipclk13>; 221*4882a593Smuzhiyun clock-output-names = "dfe-pd1"; 222*4882a593Smuzhiyun reg = <0x023500c0 0xb00>, <0x02350044 0x400>; 223*4882a593Smuzhiyun reg-names = "control", "domain"; 224*4882a593Smuzhiyun domain-id = <27>; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun clkfftc1: clkfftc1 { 228*4882a593Smuzhiyun #clock-cells = <0>; 229*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 230*4882a593Smuzhiyun clocks = <&chipclk13>; 231*4882a593Smuzhiyun clock-output-names = "fftc-1"; 232*4882a593Smuzhiyun reg = <0x023500c4 0xb00>, <0x023504c0 0x400>; 233*4882a593Smuzhiyun reg-names = "control", "domain"; 234*4882a593Smuzhiyun domain-id = <28>; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun clkiqnail: clkiqnail { 238*4882a593Smuzhiyun #clock-cells = <0>; 239*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 240*4882a593Smuzhiyun clocks = <&chipclk13>; 241*4882a593Smuzhiyun clock-output-names = "iqn-ail"; 242*4882a593Smuzhiyun reg = <0x023500c8 0xb00>, <0x0235004c 0x400>; 243*4882a593Smuzhiyun reg-names = "control", "domain"; 244*4882a593Smuzhiyun domain-id = <29>; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun clkuart2: clkuart2 { 248*4882a593Smuzhiyun #clock-cells = <0>; 249*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 250*4882a593Smuzhiyun clocks = <&clkmodrst0>; 251*4882a593Smuzhiyun clock-output-names = "uart2"; 252*4882a593Smuzhiyun reg = <0x02350000 0xb00>, <0x02350000 0x400>; 253*4882a593Smuzhiyun reg-names = "control", "domain"; 254*4882a593Smuzhiyun domain-id = <0>; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun clkuart3: clkuart3 { 258*4882a593Smuzhiyun #clock-cells = <0>; 259*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 260*4882a593Smuzhiyun clocks = <&clkmodrst0>; 261*4882a593Smuzhiyun clock-output-names = "uart3"; 262*4882a593Smuzhiyun reg = <0x02350000 0xb00>, <0x02350000 0x400>; 263*4882a593Smuzhiyun reg-names = "control", "domain"; 264*4882a593Smuzhiyun domain-id = <0>; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun}; 267