xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/keystone-k2hk-evm.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright 2013-2014 Texas Instruments, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Keystone 2 Kepler/Hawking EVM device tree
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
7*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as
8*4882a593Smuzhiyun * published by the Free Software Foundation.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun/dts-v1/;
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun#include "keystone.dtsi"
13*4882a593Smuzhiyun#include "keystone-k2hk.dtsi"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun/ {
16*4882a593Smuzhiyun	compatible =  "ti,k2hk-evm","ti,keystone";
17*4882a593Smuzhiyun	model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	soc {
20*4882a593Smuzhiyun		clocks {
21*4882a593Smuzhiyun			refclksys: refclksys {
22*4882a593Smuzhiyun				#clock-cells = <0>;
23*4882a593Smuzhiyun				compatible = "fixed-clock";
24*4882a593Smuzhiyun				clock-frequency = <122880000>;
25*4882a593Smuzhiyun				clock-output-names = "refclk-sys";
26*4882a593Smuzhiyun			};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun			refclkpass: refclkpass {
29*4882a593Smuzhiyun				#clock-cells = <0>;
30*4882a593Smuzhiyun				compatible = "fixed-clock";
31*4882a593Smuzhiyun				clock-frequency = <122880000>;
32*4882a593Smuzhiyun				clock-output-names = "refclk-pass";
33*4882a593Smuzhiyun			};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun			refclkarm: refclkarm {
36*4882a593Smuzhiyun				#clock-cells = <0>;
37*4882a593Smuzhiyun				compatible = "fixed-clock";
38*4882a593Smuzhiyun				clock-frequency = <125000000>;
39*4882a593Smuzhiyun				clock-output-names = "refclk-arm";
40*4882a593Smuzhiyun			};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun			refclkddr3a: refclkddr3a {
43*4882a593Smuzhiyun				#clock-cells = <0>;
44*4882a593Smuzhiyun				compatible = "fixed-clock";
45*4882a593Smuzhiyun				clock-frequency = <100000000>;
46*4882a593Smuzhiyun				clock-output-names = "refclk-ddr3a";
47*4882a593Smuzhiyun			};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun			refclkddr3b: refclkddr3b {
50*4882a593Smuzhiyun				#clock-cells = <0>;
51*4882a593Smuzhiyun				compatible = "fixed-clock";
52*4882a593Smuzhiyun				clock-frequency = <100000000>;
53*4882a593Smuzhiyun				clock-output-names = "refclk-ddr3b";
54*4882a593Smuzhiyun			};
55*4882a593Smuzhiyun		};
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	leds {
59*4882a593Smuzhiyun		compatible = "gpio-leds";
60*4882a593Smuzhiyun		debug1_1 {
61*4882a593Smuzhiyun			label = "keystone:green:debug1";
62*4882a593Smuzhiyun			gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
63*4882a593Smuzhiyun		};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun		debug1_2 {
66*4882a593Smuzhiyun			label = "keystone:red:debug1";
67*4882a593Smuzhiyun			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
68*4882a593Smuzhiyun		};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun		debug2 {
71*4882a593Smuzhiyun			label = "keystone:blue:debug2";
72*4882a593Smuzhiyun			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
73*4882a593Smuzhiyun		};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun		debug3 {
76*4882a593Smuzhiyun			label = "keystone:blue:debug3";
77*4882a593Smuzhiyun			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
78*4882a593Smuzhiyun		};
79*4882a593Smuzhiyun	};
80*4882a593Smuzhiyun};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun&usb_phy {
83*4882a593Smuzhiyun	status = "okay";
84*4882a593Smuzhiyun};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun&usb {
87*4882a593Smuzhiyun	status = "okay";
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun&aemif {
91*4882a593Smuzhiyun	cs0 {
92*4882a593Smuzhiyun		#address-cells = <2>;
93*4882a593Smuzhiyun		#size-cells = <1>;
94*4882a593Smuzhiyun		clock-ranges;
95*4882a593Smuzhiyun		ranges;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun		ti,cs-chipselect = <0>;
98*4882a593Smuzhiyun		/* all timings in nanoseconds */
99*4882a593Smuzhiyun		ti,cs-min-turnaround-ns = <12>;
100*4882a593Smuzhiyun		ti,cs-read-hold-ns = <6>;
101*4882a593Smuzhiyun		ti,cs-read-strobe-ns = <23>;
102*4882a593Smuzhiyun		ti,cs-read-setup-ns = <9>;
103*4882a593Smuzhiyun		ti,cs-write-hold-ns = <8>;
104*4882a593Smuzhiyun		ti,cs-write-strobe-ns = <23>;
105*4882a593Smuzhiyun		ti,cs-write-setup-ns = <8>;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun		nand@0,0 {
108*4882a593Smuzhiyun			compatible = "ti,keystone-nand","ti,davinci-nand";
109*4882a593Smuzhiyun			#address-cells = <1>;
110*4882a593Smuzhiyun			#size-cells = <1>;
111*4882a593Smuzhiyun			reg = <0 0 0x4000000
112*4882a593Smuzhiyun			       1 0 0x0000100>;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun			ti,davinci-chipselect = <0>;
115*4882a593Smuzhiyun			ti,davinci-mask-ale = <0x2000>;
116*4882a593Smuzhiyun			ti,davinci-mask-cle = <0x4000>;
117*4882a593Smuzhiyun			ti,davinci-mask-chipsel = <0>;
118*4882a593Smuzhiyun			nand-ecc-mode = "hw";
119*4882a593Smuzhiyun			ti,davinci-ecc-bits = <4>;
120*4882a593Smuzhiyun			nand-on-flash-bbt;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun			partition@0 {
123*4882a593Smuzhiyun				label = "u-boot";
124*4882a593Smuzhiyun				reg = <0x0 0x100000>;
125*4882a593Smuzhiyun				read-only;
126*4882a593Smuzhiyun			};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun			partition@100000 {
129*4882a593Smuzhiyun				label = "params";
130*4882a593Smuzhiyun				reg = <0x100000 0x80000>;
131*4882a593Smuzhiyun				read-only;
132*4882a593Smuzhiyun			};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun			partition@180000 {
135*4882a593Smuzhiyun				label = "ubifs";
136*4882a593Smuzhiyun				reg = <0x180000 0x1fe80000>;
137*4882a593Smuzhiyun			};
138*4882a593Smuzhiyun		};
139*4882a593Smuzhiyun	};
140*4882a593Smuzhiyun};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun&i2c0 {
143*4882a593Smuzhiyun	dtt@50 {
144*4882a593Smuzhiyun		compatible = "at,24c1024";
145*4882a593Smuzhiyun		reg = <0x50>;
146*4882a593Smuzhiyun	};
147*4882a593Smuzhiyun};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun&spi0 {
150*4882a593Smuzhiyun	status = "okay";
151*4882a593Smuzhiyun	nor_flash: n25q128a11@0 {
152*4882a593Smuzhiyun		#address-cells = <1>;
153*4882a593Smuzhiyun		#size-cells = <1>;
154*4882a593Smuzhiyun		compatible = "Micron,n25q128a11", "spi-flash";
155*4882a593Smuzhiyun		spi-max-frequency = <54000000>;
156*4882a593Smuzhiyun		m25p,fast-read;
157*4882a593Smuzhiyun		reg = <0>;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun		partition@0 {
160*4882a593Smuzhiyun			label = "u-boot-spl";
161*4882a593Smuzhiyun			reg = <0x0 0x80000>;
162*4882a593Smuzhiyun			read-only;
163*4882a593Smuzhiyun		};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun		partition@1 {
166*4882a593Smuzhiyun			label = "misc";
167*4882a593Smuzhiyun			reg = <0x80000 0xf80000>;
168*4882a593Smuzhiyun		};
169*4882a593Smuzhiyun	};
170*4882a593Smuzhiyun};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun&mdio {
173*4882a593Smuzhiyun	status = "ok";
174*4882a593Smuzhiyun	ethphy0: ethernet-phy@0 {
175*4882a593Smuzhiyun		compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
176*4882a593Smuzhiyun		reg = <0>;
177*4882a593Smuzhiyun	};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun	ethphy1: ethernet-phy@1 {
180*4882a593Smuzhiyun		compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
181*4882a593Smuzhiyun		reg = <1>;
182*4882a593Smuzhiyun	};
183*4882a593Smuzhiyun};
184