1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright 2014 Texas Instruments, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Keystone 2 Edison SoC specific device tree 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 7*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 8*4882a593Smuzhiyun * published by the Free Software Foundation. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyunclocks { 12*4882a593Smuzhiyun mainpllclk: mainpllclk@2310110 { 13*4882a593Smuzhiyun #clock-cells = <0>; 14*4882a593Smuzhiyun compatible = "ti,keystone,main-pll-clock"; 15*4882a593Smuzhiyun clocks = <&refclksys>; 16*4882a593Smuzhiyun reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; 17*4882a593Smuzhiyun reg-names = "control", "multiplier", "post-divider"; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun papllclk: papllclk@2620358 { 21*4882a593Smuzhiyun #clock-cells = <0>; 22*4882a593Smuzhiyun compatible = "ti,keystone,pll-clock"; 23*4882a593Smuzhiyun clocks = <&refclkpass>; 24*4882a593Smuzhiyun clock-output-names = "papllclk"; 25*4882a593Smuzhiyun reg = <0x02620358 4>; 26*4882a593Smuzhiyun reg-names = "control"; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun ddr3apllclk: ddr3apllclk@2620360 { 30*4882a593Smuzhiyun #clock-cells = <0>; 31*4882a593Smuzhiyun compatible = "ti,keystone,pll-clock"; 32*4882a593Smuzhiyun clocks = <&refclkddr3a>; 33*4882a593Smuzhiyun clock-output-names = "ddr-3a-pll-clk"; 34*4882a593Smuzhiyun reg = <0x02620360 4>; 35*4882a593Smuzhiyun reg-names = "control"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun clkusb1: clkusb1 { 39*4882a593Smuzhiyun #clock-cells = <0>; 40*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 41*4882a593Smuzhiyun clocks = <&chipclk16>; 42*4882a593Smuzhiyun clock-output-names = "usb1"; 43*4882a593Smuzhiyun reg = <0x02350004 0xb00>, <0x02350000 0x400>; 44*4882a593Smuzhiyun reg-names = "control", "domain"; 45*4882a593Smuzhiyun domain-id = <0>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun clkhyperlink0: clkhyperlink0 { 49*4882a593Smuzhiyun #clock-cells = <0>; 50*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 51*4882a593Smuzhiyun clocks = <&chipclk12>; 52*4882a593Smuzhiyun clock-output-names = "hyperlink-0"; 53*4882a593Smuzhiyun reg = <0x02350030 0xb00>, <0x02350014 0x400>; 54*4882a593Smuzhiyun reg-names = "control", "domain"; 55*4882a593Smuzhiyun domain-id = <5>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun clkpcie1: clkpcie1 { 59*4882a593Smuzhiyun #clock-cells = <0>; 60*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 61*4882a593Smuzhiyun clocks = <&chipclk12>; 62*4882a593Smuzhiyun clock-output-names = "pcie1"; 63*4882a593Smuzhiyun reg = <0x0235006c 0xb00>, <0x02350048 0x400>; 64*4882a593Smuzhiyun reg-names = "control", "domain"; 65*4882a593Smuzhiyun domain-id = <18>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun clkxge: clkxge { 69*4882a593Smuzhiyun #clock-cells = <0>; 70*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 71*4882a593Smuzhiyun clocks = <&chipclk13>; 72*4882a593Smuzhiyun clock-output-names = "xge"; 73*4882a593Smuzhiyun reg = <0x023500c8 0xb00>, <0x02350074 0x400>; 74*4882a593Smuzhiyun reg-names = "control", "domain"; 75*4882a593Smuzhiyun domain-id = <29>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun}; 78