1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Header providing constants for Rockchip suspend bindings. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2022, Rockchip Electronics Co., Ltd 6*4882a593Smuzhiyun * Author: XiaoDong.Huang 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __DT_BINDINGS_RK3528_PM_H__ 10*4882a593Smuzhiyun #define __DT_BINDINGS_RK3528_PM_H__ 11*4882a593Smuzhiyun /******************************bits ops************************************/ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef BIT 14*4882a593Smuzhiyun #define BIT(nr) (1 << (nr)) 15*4882a593Smuzhiyun #endif 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define RKPM_SLP_ARMPD BIT(0) 18*4882a593Smuzhiyun #define RKPM_SLP_ARMOFF BIT(1) 19*4882a593Smuzhiyun #define RKPM_SLP_ARMOFF_DDRPD BIT(2) 20*4882a593Smuzhiyun #define RKPM_SLP_ARMOFF_LOGOFF BIT(3) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* all plls except ddr's pll*/ 23*4882a593Smuzhiyun #define RKPM_SLP_PMU_HW_PLLS_PD BIT(8) 24*4882a593Smuzhiyun #define RKPM_SLP_PMU_PMUALIVE_32K BIT(9) 25*4882a593Smuzhiyun #define RKPM_SLP_PMU_DIS_OSC BIT(10) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define RKPM_SLP_CLK_GT BIT(16) 28*4882a593Smuzhiyun #define RKPM_SLP_PMIC_LP BIT(17) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define RKPM_SLP_32K_EXT BIT(24) 31*4882a593Smuzhiyun #define RKPM_SLP_TIME_OUT_WKUP BIT(25) 32*4882a593Smuzhiyun #define RKPM_SLP_PMU_DBG BIT(26) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* the wake up source */ 35*4882a593Smuzhiyun #define RKPM_CPU0_WKUP_EN BIT(0) 36*4882a593Smuzhiyun #define RKPM_CPU1_WKUP_EN BIT(1) 37*4882a593Smuzhiyun #define RKPM_CPU2_WKUP_EN BIT(2) 38*4882a593Smuzhiyun #define RKPM_CPU3_WKUP_EN BIT(3) 39*4882a593Smuzhiyun #define RKPM_GPIO_WKUP_EN BIT(4) 40*4882a593Smuzhiyun #define RKPM_HDMI_HDP_WKUP_EN BIT(5) 41*4882a593Smuzhiyun #define RKPM_HDMI_CEC_WKUP_EN BIT(6) 42*4882a593Smuzhiyun #define RKPM_PWMIR_WKUP_EN BIT(7) 43*4882a593Smuzhiyun #define RKPM_GMAC_WKUP_EN BIT(8) 44*4882a593Smuzhiyun #define RKPM_TIMER_WKUP_EN BIT(9) 45*4882a593Smuzhiyun #define RKPM_USBDEV_WKUP_EN BIT(10) 46*4882a593Smuzhiyun #define RKPM_SYSINT_WKUP_EN BIT(11) 47*4882a593Smuzhiyun #define RKPM_TIME_OUT_WKUP_EN BIT(12) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* the pwm regulator */ 50*4882a593Smuzhiyun #define RKPM_PWM0_M0_REGULATOR_EN BIT(0) 51*4882a593Smuzhiyun #define RKPM_PWM1_M0_REGULATOR_EN BIT(1) 52*4882a593Smuzhiyun #define RKPM_PWM2_M0_REGULATOR_EN BIT(2) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif 55