1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2015, NVIDIA CORPORATION. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ABI_MACH_T186_RESET_T186_H_ 8*4882a593Smuzhiyun #define _ABI_MACH_T186_RESET_T186_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define TEGRA186_RESET_ACTMON 0 11*4882a593Smuzhiyun #define TEGRA186_RESET_AFI 1 12*4882a593Smuzhiyun #define TEGRA186_RESET_CEC 2 13*4882a593Smuzhiyun #define TEGRA186_RESET_CSITE 3 14*4882a593Smuzhiyun #define TEGRA186_RESET_DP2 4 15*4882a593Smuzhiyun #define TEGRA186_RESET_DPAUX 5 16*4882a593Smuzhiyun #define TEGRA186_RESET_DSI 6 17*4882a593Smuzhiyun #define TEGRA186_RESET_DSIB 7 18*4882a593Smuzhiyun #define TEGRA186_RESET_DTV 8 19*4882a593Smuzhiyun #define TEGRA186_RESET_DVFS 9 20*4882a593Smuzhiyun #define TEGRA186_RESET_ENTROPY 10 21*4882a593Smuzhiyun #define TEGRA186_RESET_EXTPERIPH1 11 22*4882a593Smuzhiyun #define TEGRA186_RESET_EXTPERIPH2 12 23*4882a593Smuzhiyun #define TEGRA186_RESET_EXTPERIPH3 13 24*4882a593Smuzhiyun #define TEGRA186_RESET_GPU 14 25*4882a593Smuzhiyun #define TEGRA186_RESET_HDA 15 26*4882a593Smuzhiyun #define TEGRA186_RESET_HDA2CODEC_2X 16 27*4882a593Smuzhiyun #define TEGRA186_RESET_HDA2HDMICODEC 17 28*4882a593Smuzhiyun #define TEGRA186_RESET_HOST1X 18 29*4882a593Smuzhiyun #define TEGRA186_RESET_I2C1 19 30*4882a593Smuzhiyun #define TEGRA186_RESET_I2C2 20 31*4882a593Smuzhiyun #define TEGRA186_RESET_I2C3 21 32*4882a593Smuzhiyun #define TEGRA186_RESET_I2C4 22 33*4882a593Smuzhiyun #define TEGRA186_RESET_I2C5 23 34*4882a593Smuzhiyun #define TEGRA186_RESET_I2C6 24 35*4882a593Smuzhiyun #define TEGRA186_RESET_ISP 25 36*4882a593Smuzhiyun #define TEGRA186_RESET_KFUSE 26 37*4882a593Smuzhiyun #define TEGRA186_RESET_LA 27 38*4882a593Smuzhiyun #define TEGRA186_RESET_MIPI_CAL 28 39*4882a593Smuzhiyun #define TEGRA186_RESET_PCIE 29 40*4882a593Smuzhiyun #define TEGRA186_RESET_PCIEXCLK 30 41*4882a593Smuzhiyun #define TEGRA186_RESET_SATA 31 42*4882a593Smuzhiyun #define TEGRA186_RESET_SATACOLD 32 43*4882a593Smuzhiyun #define TEGRA186_RESET_SDMMC1 33 44*4882a593Smuzhiyun #define TEGRA186_RESET_SDMMC2 34 45*4882a593Smuzhiyun #define TEGRA186_RESET_SDMMC3 35 46*4882a593Smuzhiyun #define TEGRA186_RESET_SDMMC4 36 47*4882a593Smuzhiyun #define TEGRA186_RESET_SE 37 48*4882a593Smuzhiyun #define TEGRA186_RESET_SOC_THERM 38 49*4882a593Smuzhiyun #define TEGRA186_RESET_SOR0 39 50*4882a593Smuzhiyun #define TEGRA186_RESET_SPI1 40 51*4882a593Smuzhiyun #define TEGRA186_RESET_SPI2 41 52*4882a593Smuzhiyun #define TEGRA186_RESET_SPI3 42 53*4882a593Smuzhiyun #define TEGRA186_RESET_SPI4 43 54*4882a593Smuzhiyun #define TEGRA186_RESET_TMR 44 55*4882a593Smuzhiyun #define TEGRA186_RESET_TRIG_SYS 45 56*4882a593Smuzhiyun #define TEGRA186_RESET_TSEC 46 57*4882a593Smuzhiyun #define TEGRA186_RESET_UARTA 47 58*4882a593Smuzhiyun #define TEGRA186_RESET_UARTB 48 59*4882a593Smuzhiyun #define TEGRA186_RESET_UARTC 49 60*4882a593Smuzhiyun #define TEGRA186_RESET_UARTD 50 61*4882a593Smuzhiyun #define TEGRA186_RESET_VI 51 62*4882a593Smuzhiyun #define TEGRA186_RESET_VIC 52 63*4882a593Smuzhiyun #define TEGRA186_RESET_XUSB_DEV 53 64*4882a593Smuzhiyun #define TEGRA186_RESET_XUSB_HOST 54 65*4882a593Smuzhiyun #define TEGRA186_RESET_XUSB_PADCTL 55 66*4882a593Smuzhiyun #define TEGRA186_RESET_XUSB_SS 56 67*4882a593Smuzhiyun #define TEGRA186_RESET_AON_APB 57 68*4882a593Smuzhiyun #define TEGRA186_RESET_AXI_CBB 58 69*4882a593Smuzhiyun #define TEGRA186_RESET_BPMP_APB 59 70*4882a593Smuzhiyun #define TEGRA186_RESET_CAN1 60 71*4882a593Smuzhiyun #define TEGRA186_RESET_CAN2 61 72*4882a593Smuzhiyun #define TEGRA186_RESET_DMIC5 62 73*4882a593Smuzhiyun #define TEGRA186_RESET_DSIC 63 74*4882a593Smuzhiyun #define TEGRA186_RESET_DSID 64 75*4882a593Smuzhiyun #define TEGRA186_RESET_EMC_EMC 65 76*4882a593Smuzhiyun #define TEGRA186_RESET_EMC_MEM 66 77*4882a593Smuzhiyun #define TEGRA186_RESET_EMCSB_EMC 67 78*4882a593Smuzhiyun #define TEGRA186_RESET_EMCSB_MEM 68 79*4882a593Smuzhiyun #define TEGRA186_RESET_EQOS 69 80*4882a593Smuzhiyun #define TEGRA186_RESET_GPCDMA 70 81*4882a593Smuzhiyun #define TEGRA186_RESET_GPIO_CTL0 71 82*4882a593Smuzhiyun #define TEGRA186_RESET_GPIO_CTL1 72 83*4882a593Smuzhiyun #define TEGRA186_RESET_GPIO_CTL2 73 84*4882a593Smuzhiyun #define TEGRA186_RESET_GPIO_CTL3 74 85*4882a593Smuzhiyun #define TEGRA186_RESET_GPIO_CTL4 75 86*4882a593Smuzhiyun #define TEGRA186_RESET_GPIO_CTL5 76 87*4882a593Smuzhiyun #define TEGRA186_RESET_I2C10 77 88*4882a593Smuzhiyun #define TEGRA186_RESET_I2C12 78 89*4882a593Smuzhiyun #define TEGRA186_RESET_I2C13 79 90*4882a593Smuzhiyun #define TEGRA186_RESET_I2C14 80 91*4882a593Smuzhiyun #define TEGRA186_RESET_I2C7 81 92*4882a593Smuzhiyun #define TEGRA186_RESET_I2C8 82 93*4882a593Smuzhiyun #define TEGRA186_RESET_I2C9 83 94*4882a593Smuzhiyun #define TEGRA186_RESET_JTAG2AXI 84 95*4882a593Smuzhiyun #define TEGRA186_RESET_MPHY_IOBIST 85 96*4882a593Smuzhiyun #define TEGRA186_RESET_MPHY_L0_RX 86 97*4882a593Smuzhiyun #define TEGRA186_RESET_MPHY_L0_TX 87 98*4882a593Smuzhiyun #define TEGRA186_RESET_NVCSI 88 99*4882a593Smuzhiyun #define TEGRA186_RESET_NVDISPLAY0_HEAD0 89 100*4882a593Smuzhiyun #define TEGRA186_RESET_NVDISPLAY0_HEAD1 90 101*4882a593Smuzhiyun #define TEGRA186_RESET_NVDISPLAY0_HEAD2 91 102*4882a593Smuzhiyun #define TEGRA186_RESET_NVDISPLAY0_MISC 92 103*4882a593Smuzhiyun #define TEGRA186_RESET_NVDISPLAY0_WGRP0 93 104*4882a593Smuzhiyun #define TEGRA186_RESET_NVDISPLAY0_WGRP1 94 105*4882a593Smuzhiyun #define TEGRA186_RESET_NVDISPLAY0_WGRP2 95 106*4882a593Smuzhiyun #define TEGRA186_RESET_NVDISPLAY0_WGRP3 96 107*4882a593Smuzhiyun #define TEGRA186_RESET_NVDISPLAY0_WGRP4 97 108*4882a593Smuzhiyun #define TEGRA186_RESET_NVDISPLAY0_WGRP5 98 109*4882a593Smuzhiyun #define TEGRA186_RESET_PWM1 99 110*4882a593Smuzhiyun #define TEGRA186_RESET_PWM2 100 111*4882a593Smuzhiyun #define TEGRA186_RESET_PWM3 101 112*4882a593Smuzhiyun #define TEGRA186_RESET_PWM4 102 113*4882a593Smuzhiyun #define TEGRA186_RESET_PWM5 103 114*4882a593Smuzhiyun #define TEGRA186_RESET_PWM6 104 115*4882a593Smuzhiyun #define TEGRA186_RESET_PWM7 105 116*4882a593Smuzhiyun #define TEGRA186_RESET_PWM8 106 117*4882a593Smuzhiyun #define TEGRA186_RESET_SCE_APB 107 118*4882a593Smuzhiyun #define TEGRA186_RESET_SOR1 108 119*4882a593Smuzhiyun #define TEGRA186_RESET_TACH 109 120*4882a593Smuzhiyun #define TEGRA186_RESET_TSC 110 121*4882a593Smuzhiyun #define TEGRA186_RESET_UARTF 111 122*4882a593Smuzhiyun #define TEGRA186_RESET_UARTG 112 123*4882a593Smuzhiyun #define TEGRA186_RESET_UFSHC 113 124*4882a593Smuzhiyun #define TEGRA186_RESET_UFSHC_AXI_M 114 125*4882a593Smuzhiyun #define TEGRA186_RESET_UPHY 115 126*4882a593Smuzhiyun #define TEGRA186_RESET_ADSP 116 127*4882a593Smuzhiyun #define TEGRA186_RESET_ADSPDBG 117 128*4882a593Smuzhiyun #define TEGRA186_RESET_ADSPINTF 118 129*4882a593Smuzhiyun #define TEGRA186_RESET_ADSPNEON 119 130*4882a593Smuzhiyun #define TEGRA186_RESET_ADSPPERIPH 120 131*4882a593Smuzhiyun #define TEGRA186_RESET_ADSPSCU 121 132*4882a593Smuzhiyun #define TEGRA186_RESET_ADSPWDT 122 133*4882a593Smuzhiyun #define TEGRA186_RESET_APE 123 134*4882a593Smuzhiyun #define TEGRA186_RESET_DPAUX1 124 135*4882a593Smuzhiyun #define TEGRA186_RESET_NVDEC 125 136*4882a593Smuzhiyun #define TEGRA186_RESET_NVENC 126 137*4882a593Smuzhiyun #define TEGRA186_RESET_NVJPG 127 138*4882a593Smuzhiyun #define TEGRA186_RESET_PEX_USB_UPHY 128 139*4882a593Smuzhiyun #define TEGRA186_RESET_QSPI 129 140*4882a593Smuzhiyun #define TEGRA186_RESET_TSECB 130 141*4882a593Smuzhiyun #define TEGRA186_RESET_VI_I2C 131 142*4882a593Smuzhiyun #define TEGRA186_RESET_UARTE 132 143*4882a593Smuzhiyun #define TEGRA186_RESET_TOP_GTE 133 144*4882a593Smuzhiyun #define TEGRA186_RESET_SHSP 134 145*4882a593Smuzhiyun #define TEGRA186_RESET_PEX_USB_UPHY_L5 135 146*4882a593Smuzhiyun #define TEGRA186_RESET_PEX_USB_UPHY_L4 136 147*4882a593Smuzhiyun #define TEGRA186_RESET_PEX_USB_UPHY_L3 137 148*4882a593Smuzhiyun #define TEGRA186_RESET_PEX_USB_UPHY_L2 138 149*4882a593Smuzhiyun #define TEGRA186_RESET_PEX_USB_UPHY_L1 139 150*4882a593Smuzhiyun #define TEGRA186_RESET_PEX_USB_UPHY_L0 140 151*4882a593Smuzhiyun #define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141 152*4882a593Smuzhiyun #define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142 153*4882a593Smuzhiyun #define TEGRA186_RESET_TSCTNVI 143 154*4882a593Smuzhiyun #define TEGRA186_RESET_EXTPERIPH4 144 155*4882a593Smuzhiyun #define TEGRA186_RESET_DSIPADCTL 145 156*4882a593Smuzhiyun #define TEGRA186_RESET_AUD_MCLK 146 157*4882a593Smuzhiyun #define TEGRA186_RESET_MPHY_CLK_CTL 147 158*4882a593Smuzhiyun #define TEGRA186_RESET_MPHY_L1_RX 148 159*4882a593Smuzhiyun #define TEGRA186_RESET_MPHY_L1_TX 149 160*4882a593Smuzhiyun #define TEGRA186_RESET_UFSHC_LP 150 161*4882a593Smuzhiyun #define TEGRA186_RESET_BPMP_NIC 151 162*4882a593Smuzhiyun #define TEGRA186_RESET_BPMP_NSYSPORESET 152 163*4882a593Smuzhiyun #define TEGRA186_RESET_BPMP_NRESET 153 164*4882a593Smuzhiyun #define TEGRA186_RESET_BPMP_DBGRESETN 154 165*4882a593Smuzhiyun #define TEGRA186_RESET_BPMP_PRESETDBGN 155 166*4882a593Smuzhiyun #define TEGRA186_RESET_BPMP_PM 156 167*4882a593Smuzhiyun #define TEGRA186_RESET_BPMP_CVC 157 168*4882a593Smuzhiyun #define TEGRA186_RESET_BPMP_DMA 158 169*4882a593Smuzhiyun #define TEGRA186_RESET_BPMP_HSP 159 170*4882a593Smuzhiyun #define TEGRA186_RESET_TSCTNBPMP 160 171*4882a593Smuzhiyun #define TEGRA186_RESET_BPMP_TKE 161 172*4882a593Smuzhiyun #define TEGRA186_RESET_BPMP_GTE 162 173*4882a593Smuzhiyun #define TEGRA186_RESET_BPMP_PM_ACTMON 163 174*4882a593Smuzhiyun #define TEGRA186_RESET_AON_NIC 164 175*4882a593Smuzhiyun #define TEGRA186_RESET_AON_NSYSPORESET 165 176*4882a593Smuzhiyun #define TEGRA186_RESET_AON_NRESET 166 177*4882a593Smuzhiyun #define TEGRA186_RESET_AON_DBGRESETN 167 178*4882a593Smuzhiyun #define TEGRA186_RESET_AON_PRESETDBGN 168 179*4882a593Smuzhiyun #define TEGRA186_RESET_AON_ACTMON 169 180*4882a593Smuzhiyun #define TEGRA186_RESET_AOPM 170 181*4882a593Smuzhiyun #define TEGRA186_RESET_AOVC 171 182*4882a593Smuzhiyun #define TEGRA186_RESET_AON_DMA 172 183*4882a593Smuzhiyun #define TEGRA186_RESET_AON_GPIO 173 184*4882a593Smuzhiyun #define TEGRA186_RESET_AON_HSP 174 185*4882a593Smuzhiyun #define TEGRA186_RESET_TSCTNAON 175 186*4882a593Smuzhiyun #define TEGRA186_RESET_AON_TKE 176 187*4882a593Smuzhiyun #define TEGRA186_RESET_AON_GTE 177 188*4882a593Smuzhiyun #define TEGRA186_RESET_SCE_NIC 178 189*4882a593Smuzhiyun #define TEGRA186_RESET_SCE_NSYSPORESET 179 190*4882a593Smuzhiyun #define TEGRA186_RESET_SCE_NRESET 180 191*4882a593Smuzhiyun #define TEGRA186_RESET_SCE_DBGRESETN 181 192*4882a593Smuzhiyun #define TEGRA186_RESET_SCE_PRESETDBGN 182 193*4882a593Smuzhiyun #define TEGRA186_RESET_SCE_ACTMON 183 194*4882a593Smuzhiyun #define TEGRA186_RESET_SCE_PM 184 195*4882a593Smuzhiyun #define TEGRA186_RESET_SCE_DMA 185 196*4882a593Smuzhiyun #define TEGRA186_RESET_SCE_HSP 186 197*4882a593Smuzhiyun #define TEGRA186_RESET_TSCTNSCE 187 198*4882a593Smuzhiyun #define TEGRA186_RESET_SCE_TKE 188 199*4882a593Smuzhiyun #define TEGRA186_RESET_SCE_GTE 189 200*4882a593Smuzhiyun #define TEGRA186_RESET_SCE_CFG 190 201*4882a593Smuzhiyun #define TEGRA186_RESET_ADSP_ALL 191 202*4882a593Smuzhiyun /** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */ 203*4882a593Smuzhiyun #define TEGRA186_RESET_UFSHC_LP_SEQ 192 204*4882a593Smuzhiyun #define TEGRA186_RESET_SIZE 193 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #endif 207