1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This header provides constants for the reset controller 3*4882a593Smuzhiyun * based peripheral powerdown requests on the STMicroelectronics 4*4882a593Smuzhiyun * STiH407 SoC. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407 7*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_CONTROLLER_STIH407 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* Powerdown requests control 0 */ 10*4882a593Smuzhiyun #define STIH407_EMISS_POWERDOWN 0 11*4882a593Smuzhiyun #define STIH407_NAND_POWERDOWN 1 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Synp GMAC PowerDown */ 14*4882a593Smuzhiyun #define STIH407_ETH1_POWERDOWN 2 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Powerdown requests control 1 */ 17*4882a593Smuzhiyun #define STIH407_USB3_POWERDOWN 3 18*4882a593Smuzhiyun #define STIH407_USB2_PORT1_POWERDOWN 4 19*4882a593Smuzhiyun #define STIH407_USB2_PORT0_POWERDOWN 5 20*4882a593Smuzhiyun #define STIH407_PCIE1_POWERDOWN 6 21*4882a593Smuzhiyun #define STIH407_PCIE0_POWERDOWN 7 22*4882a593Smuzhiyun #define STIH407_SATA1_POWERDOWN 8 23*4882a593Smuzhiyun #define STIH407_SATA0_POWERDOWN 9 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Reset defines */ 26*4882a593Smuzhiyun #define STIH407_ETH1_SOFTRESET 0 27*4882a593Smuzhiyun #define STIH407_MMC1_SOFTRESET 1 28*4882a593Smuzhiyun #define STIH407_PICOPHY_SOFTRESET 2 29*4882a593Smuzhiyun #define STIH407_IRB_SOFTRESET 3 30*4882a593Smuzhiyun #define STIH407_PCIE0_SOFTRESET 4 31*4882a593Smuzhiyun #define STIH407_PCIE1_SOFTRESET 5 32*4882a593Smuzhiyun #define STIH407_SATA0_SOFTRESET 6 33*4882a593Smuzhiyun #define STIH407_SATA1_SOFTRESET 7 34*4882a593Smuzhiyun #define STIH407_MIPHY0_SOFTRESET 8 35*4882a593Smuzhiyun #define STIH407_MIPHY1_SOFTRESET 9 36*4882a593Smuzhiyun #define STIH407_MIPHY2_SOFTRESET 10 37*4882a593Smuzhiyun #define STIH407_SATA0_PWR_SOFTRESET 11 38*4882a593Smuzhiyun #define STIH407_SATA1_PWR_SOFTRESET 12 39*4882a593Smuzhiyun #define STIH407_DELTA_SOFTRESET 13 40*4882a593Smuzhiyun #define STIH407_BLITTER_SOFTRESET 14 41*4882a593Smuzhiyun #define STIH407_HDTVOUT_SOFTRESET 15 42*4882a593Smuzhiyun #define STIH407_HDQVDP_SOFTRESET 16 43*4882a593Smuzhiyun #define STIH407_VDP_AUX_SOFTRESET 17 44*4882a593Smuzhiyun #define STIH407_COMPO_SOFTRESET 18 45*4882a593Smuzhiyun #define STIH407_HDMI_TX_PHY_SOFTRESET 19 46*4882a593Smuzhiyun #define STIH407_JPEG_DEC_SOFTRESET 20 47*4882a593Smuzhiyun #define STIH407_VP8_DEC_SOFTRESET 21 48*4882a593Smuzhiyun #define STIH407_GPU_SOFTRESET 22 49*4882a593Smuzhiyun #define STIH407_HVA_SOFTRESET 23 50*4882a593Smuzhiyun #define STIH407_ERAM_HVA_SOFTRESET 24 51*4882a593Smuzhiyun #define STIH407_LPM_SOFTRESET 25 52*4882a593Smuzhiyun #define STIH407_KEYSCAN_SOFTRESET 26 53*4882a593Smuzhiyun #define STIH407_USB2_PORT0_SOFTRESET 27 54*4882a593Smuzhiyun #define STIH407_USB2_PORT1_SOFTRESET 28 55*4882a593Smuzhiyun #define STIH407_ST231_AUD_SOFTRESET 29 56*4882a593Smuzhiyun #define STIH407_ST231_DMU_SOFTRESET 30 57*4882a593Smuzhiyun #define STIH407_ST231_GP0_SOFTRESET 31 58*4882a593Smuzhiyun #define STIH407_ST231_GP1_SOFTRESET 32 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Picophy reset defines */ 61*4882a593Smuzhiyun #define STIH407_PICOPHY0_RESET 0 62*4882a593Smuzhiyun #define STIH407_PICOPHY1_RESET 1 63*4882a593Smuzhiyun #define STIH407_PICOPHY2_RESET 2 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */ 66