1*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__ 2*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_RK3399_POWER_H__ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* VD_CORE_L */ 5*4882a593Smuzhiyun #define RK3399_PD_A53_L0 0 6*4882a593Smuzhiyun #define RK3399_PD_A53_L1 1 7*4882a593Smuzhiyun #define RK3399_PD_A53_L2 2 8*4882a593Smuzhiyun #define RK3399_PD_A53_L3 3 9*4882a593Smuzhiyun #define RK3399_PD_SCU_L 4 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* VD_CORE_B */ 12*4882a593Smuzhiyun #define RK3399_PD_A72_B0 5 13*4882a593Smuzhiyun #define RK3399_PD_A72_B1 6 14*4882a593Smuzhiyun #define RK3399_PD_SCU_B 7 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* VD_LOGIC */ 17*4882a593Smuzhiyun #define RK3399_PD_TCPD0 8 18*4882a593Smuzhiyun #define RK3399_PD_TCPD1 9 19*4882a593Smuzhiyun #define RK3399_PD_CCI 10 20*4882a593Smuzhiyun #define RK3399_PD_CCI0 11 21*4882a593Smuzhiyun #define RK3399_PD_CCI1 12 22*4882a593Smuzhiyun #define RK3399_PD_PERILP 13 23*4882a593Smuzhiyun #define RK3399_PD_PERIHP 14 24*4882a593Smuzhiyun #define RK3399_PD_VIO 15 25*4882a593Smuzhiyun #define RK3399_PD_VO 16 26*4882a593Smuzhiyun #define RK3399_PD_VOPB 17 27*4882a593Smuzhiyun #define RK3399_PD_VOPL 18 28*4882a593Smuzhiyun #define RK3399_PD_ISP0 19 29*4882a593Smuzhiyun #define RK3399_PD_ISP1 20 30*4882a593Smuzhiyun #define RK3399_PD_HDCP 21 31*4882a593Smuzhiyun #define RK3399_PD_GMAC 22 32*4882a593Smuzhiyun #define RK3399_PD_EMMC 23 33*4882a593Smuzhiyun #define RK3399_PD_USB3 24 34*4882a593Smuzhiyun #define RK3399_PD_EDP 25 35*4882a593Smuzhiyun #define RK3399_PD_GIC 26 36*4882a593Smuzhiyun #define RK3399_PD_SD 27 37*4882a593Smuzhiyun #define RK3399_PD_SDIOAUDIO 28 38*4882a593Smuzhiyun #define RK3399_PD_ALIVE 29 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* VD_CENTER */ 41*4882a593Smuzhiyun #define RK3399_PD_CENTER 30 42*4882a593Smuzhiyun #define RK3399_PD_VCODEC 31 43*4882a593Smuzhiyun #define RK3399_PD_VDU 32 44*4882a593Smuzhiyun #define RK3399_PD_RGA 33 45*4882a593Smuzhiyun #define RK3399_PD_IEP 34 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* VD_GPU */ 48*4882a593Smuzhiyun #define RK3399_PD_GPU 35 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* VD_PMU */ 51*4882a593Smuzhiyun #define RK3399_PD_PMU 36 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #endif 54