1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2014 MundoReader S.L. 3*4882a593Smuzhiyun * Author: Heiko Stuebner <heiko@sntech.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H 9*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* core clocks */ 12*4882a593Smuzhiyun #define PLL_APLL 1 13*4882a593Smuzhiyun #define PLL_DPLL 2 14*4882a593Smuzhiyun #define PLL_GPLL 3 15*4882a593Smuzhiyun #define ARMCLK 4 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* sclk gates (special clocks) */ 18*4882a593Smuzhiyun #define SCLK_GPU 64 19*4882a593Smuzhiyun #define SCLK_SPI 65 20*4882a593Smuzhiyun #define SCLK_SDMMC 68 21*4882a593Smuzhiyun #define SCLK_SDIO 69 22*4882a593Smuzhiyun #define SCLK_EMMC 71 23*4882a593Smuzhiyun #define SCLK_NANDC 76 24*4882a593Smuzhiyun #define SCLK_UART0 77 25*4882a593Smuzhiyun #define SCLK_UART1 78 26*4882a593Smuzhiyun #define SCLK_UART2 79 27*4882a593Smuzhiyun #define SCLK_I2S 82 28*4882a593Smuzhiyun #define SCLK_SPDIF 83 29*4882a593Smuzhiyun #define SCLK_TIMER0 85 30*4882a593Smuzhiyun #define SCLK_TIMER1 86 31*4882a593Smuzhiyun #define SCLK_TIMER2 87 32*4882a593Smuzhiyun #define SCLK_TIMER3 88 33*4882a593Smuzhiyun #define SCLK_OTGPHY0 93 34*4882a593Smuzhiyun #define SCLK_LCDC 100 35*4882a593Smuzhiyun #define SCLK_HDMI 109 36*4882a593Smuzhiyun #define SCLK_HEVC 111 37*4882a593Smuzhiyun #define SCLK_I2S_OUT 113 38*4882a593Smuzhiyun #define SCLK_SDMMC_DRV 114 39*4882a593Smuzhiyun #define SCLK_SDIO_DRV 115 40*4882a593Smuzhiyun #define SCLK_EMMC_DRV 117 41*4882a593Smuzhiyun #define SCLK_SDMMC_SAMPLE 118 42*4882a593Smuzhiyun #define SCLK_SDIO_SAMPLE 119 43*4882a593Smuzhiyun #define SCLK_EMMC_SAMPLE 121 44*4882a593Smuzhiyun #define SCLK_PVTM_CORE 123 45*4882a593Smuzhiyun #define SCLK_PVTM_GPU 124 46*4882a593Smuzhiyun #define SCLK_PVTM_VIDEO 125 47*4882a593Smuzhiyun #define SCLK_MAC 151 48*4882a593Smuzhiyun #define SCLK_MACREF 152 49*4882a593Smuzhiyun #define SCLK_SFC 160 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define DCLK_LCDC 190 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* aclk gates */ 54*4882a593Smuzhiyun #define ACLK_DMAC2 194 55*4882a593Smuzhiyun #define ACLK_LCDC 197 56*4882a593Smuzhiyun #define ACLK_VIO 203 57*4882a593Smuzhiyun #define ACLK_VCODEC 208 58*4882a593Smuzhiyun #define ACLK_CPU 209 59*4882a593Smuzhiyun #define ACLK_PERI 210 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* pclk gates */ 62*4882a593Smuzhiyun #define PCLK_GPIO0 320 63*4882a593Smuzhiyun #define PCLK_GPIO1 321 64*4882a593Smuzhiyun #define PCLK_GPIO2 322 65*4882a593Smuzhiyun #define PCLK_GRF 329 66*4882a593Smuzhiyun #define PCLK_I2C0 332 67*4882a593Smuzhiyun #define PCLK_I2C1 333 68*4882a593Smuzhiyun #define PCLK_I2C2 334 69*4882a593Smuzhiyun #define PCLK_SPI 338 70*4882a593Smuzhiyun #define PCLK_UART0 341 71*4882a593Smuzhiyun #define PCLK_UART1 342 72*4882a593Smuzhiyun #define PCLK_UART2 343 73*4882a593Smuzhiyun #define PCLK_PWM 350 74*4882a593Smuzhiyun #define PCLK_TIMER 353 75*4882a593Smuzhiyun #define PCLK_HDMI 360 76*4882a593Smuzhiyun #define PCLK_CPU 362 77*4882a593Smuzhiyun #define PCLK_PERI 363 78*4882a593Smuzhiyun #define PCLK_DDRUPCTL 364 79*4882a593Smuzhiyun #define PCLK_WDT 368 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* hclk gates */ 82*4882a593Smuzhiyun #define HCLK_OTG0 449 83*4882a593Smuzhiyun #define HCLK_OTG1 450 84*4882a593Smuzhiyun #define HCLK_NANDC 453 85*4882a593Smuzhiyun #define HCLK_SFC 454 86*4882a593Smuzhiyun #define HCLK_SDMMC 456 87*4882a593Smuzhiyun #define HCLK_SDIO 457 88*4882a593Smuzhiyun #define HCLK_EMMC 459 89*4882a593Smuzhiyun #define HCLK_I2S 462 90*4882a593Smuzhiyun #define HCLK_LCDC 465 91*4882a593Smuzhiyun #define HCLK_ROM 467 92*4882a593Smuzhiyun #define HCLK_VIO_BUS 472 93*4882a593Smuzhiyun #define HCLK_VCODEC 476 94*4882a593Smuzhiyun #define HCLK_CPU 477 95*4882a593Smuzhiyun #define HCLK_PERI 478 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define CLK_NR_CLKS (HCLK_PERI + 1) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* soft-reset indices */ 100*4882a593Smuzhiyun #define SRST_CORE0 0 101*4882a593Smuzhiyun #define SRST_CORE1 1 102*4882a593Smuzhiyun #define SRST_CORE0_DBG 4 103*4882a593Smuzhiyun #define SRST_CORE1_DBG 5 104*4882a593Smuzhiyun #define SRST_CORE0_POR 8 105*4882a593Smuzhiyun #define SRST_CORE1_POR 9 106*4882a593Smuzhiyun #define SRST_L2C 12 107*4882a593Smuzhiyun #define SRST_TOPDBG 13 108*4882a593Smuzhiyun #define SRST_STRC_SYS_A 14 109*4882a593Smuzhiyun #define SRST_PD_CORE_NIU 15 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define SRST_TIMER2 16 112*4882a593Smuzhiyun #define SRST_CPUSYS_H 17 113*4882a593Smuzhiyun #define SRST_AHB2APB_H 19 114*4882a593Smuzhiyun #define SRST_TIMER3 20 115*4882a593Smuzhiyun #define SRST_INTMEM 21 116*4882a593Smuzhiyun #define SRST_ROM 22 117*4882a593Smuzhiyun #define SRST_PERI_NIU 23 118*4882a593Smuzhiyun #define SRST_I2S 24 119*4882a593Smuzhiyun #define SRST_DDR_PLL 25 120*4882a593Smuzhiyun #define SRST_GPU_DLL 26 121*4882a593Smuzhiyun #define SRST_TIMER0 27 122*4882a593Smuzhiyun #define SRST_TIMER1 28 123*4882a593Smuzhiyun #define SRST_CORE_DLL 29 124*4882a593Smuzhiyun #define SRST_EFUSE_P 30 125*4882a593Smuzhiyun #define SRST_ACODEC_P 31 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define SRST_GPIO0 32 128*4882a593Smuzhiyun #define SRST_GPIO1 33 129*4882a593Smuzhiyun #define SRST_GPIO2 34 130*4882a593Smuzhiyun #define SRST_UART0 39 131*4882a593Smuzhiyun #define SRST_UART1 40 132*4882a593Smuzhiyun #define SRST_UART2 41 133*4882a593Smuzhiyun #define SRST_I2C0 43 134*4882a593Smuzhiyun #define SRST_I2C1 44 135*4882a593Smuzhiyun #define SRST_I2C2 45 136*4882a593Smuzhiyun #define SRST_SFC 47 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define SRST_PWM0 48 139*4882a593Smuzhiyun #define SRST_DAP 51 140*4882a593Smuzhiyun #define SRST_DAP_SYS 52 141*4882a593Smuzhiyun #define SRST_GRF 55 142*4882a593Smuzhiyun #define SRST_PERIPHSYS_A 57 143*4882a593Smuzhiyun #define SRST_PERIPHSYS_H 58 144*4882a593Smuzhiyun #define SRST_PERIPHSYS_P 59 145*4882a593Smuzhiyun #define SRST_CPU_PERI 61 146*4882a593Smuzhiyun #define SRST_EMEM_PERI 62 147*4882a593Smuzhiyun #define SRST_USB_PERI 63 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define SRST_DMA2 64 150*4882a593Smuzhiyun #define SRST_MAC 66 151*4882a593Smuzhiyun #define SRST_NANDC 68 152*4882a593Smuzhiyun #define SRST_USBOTG0 69 153*4882a593Smuzhiyun #define SRST_OTGC0 71 154*4882a593Smuzhiyun #define SRST_USBOTG1 72 155*4882a593Smuzhiyun #define SRST_OTGC1 74 156*4882a593Smuzhiyun #define SRST_DDRMSCH 79 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define SRST_MMC0 81 159*4882a593Smuzhiyun #define SRST_SDIO 82 160*4882a593Smuzhiyun #define SRST_EMMC 83 161*4882a593Smuzhiyun #define SRST_SPI0 84 162*4882a593Smuzhiyun #define SRST_WDT 86 163*4882a593Smuzhiyun #define SRST_DDRPHY 88 164*4882a593Smuzhiyun #define SRST_DDRPHY_P 89 165*4882a593Smuzhiyun #define SRST_DDRCTRL 90 166*4882a593Smuzhiyun #define SRST_DDRCTRL_P 91 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun #define SRST_HDMI_P 96 169*4882a593Smuzhiyun #define SRST_VIO_BUS_H 99 170*4882a593Smuzhiyun #define SRST_UTMI0 103 171*4882a593Smuzhiyun #define SRST_UTMI1 104 172*4882a593Smuzhiyun #define SRST_USBPOR 105 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define SRST_VCODEC_A 112 175*4882a593Smuzhiyun #define SRST_VCODEC_H 113 176*4882a593Smuzhiyun #define SRST_VIO1_A 114 177*4882a593Smuzhiyun #define SRST_HEVC 115 178*4882a593Smuzhiyun #define SRST_VCODEC_NIU_A 116 179*4882a593Smuzhiyun #define SRST_LCDC1_A 117 180*4882a593Smuzhiyun #define SRST_LCDC1_H 118 181*4882a593Smuzhiyun #define SRST_LCDC1_D 119 182*4882a593Smuzhiyun #define SRST_GPU 120 183*4882a593Smuzhiyun #define SRST_GPU_NIU_A 122 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #define SRST_DBG_P 131 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #endif 188