1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 6*4882a593Smuzhiyun * published by the Free Software Foundation. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H 11*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX6SLL_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define IMX6SLL_CLK_DUMMY 0 14*4882a593Smuzhiyun #define IMX6SLL_CLK_CKIL 1 15*4882a593Smuzhiyun #define IMX6SLL_CLK_OSC 2 16*4882a593Smuzhiyun #define IMX6SLL_PLL1_BYPASS_SRC 3 17*4882a593Smuzhiyun #define IMX6SLL_PLL2_BYPASS_SRC 4 18*4882a593Smuzhiyun #define IMX6SLL_PLL3_BYPASS_SRC 5 19*4882a593Smuzhiyun #define IMX6SLL_PLL4_BYPASS_SRC 6 20*4882a593Smuzhiyun #define IMX6SLL_PLL5_BYPASS_SRC 7 21*4882a593Smuzhiyun #define IMX6SLL_PLL6_BYPASS_SRC 8 22*4882a593Smuzhiyun #define IMX6SLL_PLL7_BYPASS_SRC 9 23*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL1 10 24*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2 11 25*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3 12 26*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL4 13 27*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL5 14 28*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL6 15 29*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL7 16 30*4882a593Smuzhiyun #define IMX6SLL_PLL1_BYPASS 17 31*4882a593Smuzhiyun #define IMX6SLL_PLL2_BYPASS 18 32*4882a593Smuzhiyun #define IMX6SLL_PLL3_BYPASS 19 33*4882a593Smuzhiyun #define IMX6SLL_PLL4_BYPASS 20 34*4882a593Smuzhiyun #define IMX6SLL_PLL5_BYPASS 21 35*4882a593Smuzhiyun #define IMX6SLL_PLL6_BYPASS 22 36*4882a593Smuzhiyun #define IMX6SLL_PLL7_BYPASS 23 37*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL1_SYS 24 38*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2_BUS 25 39*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_USB_OTG 26 40*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL4_AUDIO 27 41*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL5_VIDEO 28 42*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL6_ENET 29 43*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL7_USB_HOST 30 44*4882a593Smuzhiyun #define IMX6SLL_CLK_USBPHY1 31 45*4882a593Smuzhiyun #define IMX6SLL_CLK_USBPHY2 32 46*4882a593Smuzhiyun #define IMX6SLL_CLK_USBPHY1_GATE 33 47*4882a593Smuzhiyun #define IMX6SLL_CLK_USBPHY2_GATE 34 48*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2_PFD0 35 49*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2_PFD1 36 50*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2_PFD2 37 51*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2_PFD3 38 52*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_PFD0 39 53*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_PFD1 40 54*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_PFD2 41 55*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_PFD3 42 56*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL4_POST_DIV 43 57*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL4_AUDIO_DIV 44 58*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL5_POST_DIV 45 59*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 60*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2_198M 47 61*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_120M 48 62*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_80M 49 63*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_60M 50 64*4882a593Smuzhiyun #define IMX6SLL_CLK_STEP 51 65*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL1_SW 52 66*4882a593Smuzhiyun #define IMX6SLL_CLK_AXI_ALT_SEL 53 67*4882a593Smuzhiyun #define IMX6SLL_CLK_AXI_SEL 54 68*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH_PRE 55 69*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH2_PRE 56 70*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH_CLK2_SEL 57 71*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58 72*4882a593Smuzhiyun #define IMX6SLL_CLK_PERCLK_SEL 59 73*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC1_SEL 60 74*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC2_SEL 61 75*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC3_SEL 62 76*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI1_SEL 63 77*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI2_SEL 64 78*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI3_SEL 65 79*4882a593Smuzhiyun #define IMX6SLL_CLK_PXP_SEL 66 80*4882a593Smuzhiyun #define IMX6SLL_CLK_LCDIF_PRE_SEL 67 81*4882a593Smuzhiyun #define IMX6SLL_CLK_LCDIF_SEL 68 82*4882a593Smuzhiyun #define IMX6SLL_CLK_EPDC_PRE_SEL 69 83*4882a593Smuzhiyun #define IMX6SLL_CLK_SPDIF_SEL 70 84*4882a593Smuzhiyun #define IMX6SLL_CLK_ECSPI_SEL 71 85*4882a593Smuzhiyun #define IMX6SLL_CLK_UART_SEL 72 86*4882a593Smuzhiyun #define IMX6SLL_CLK_ARM 73 87*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH 74 88*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH2 75 89*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH2_CLK2 76 90*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH_CLK2 77 91*4882a593Smuzhiyun #define IMX6SLL_CLK_MMDC_PODF 78 92*4882a593Smuzhiyun #define IMX6SLL_CLK_AXI_PODF 79 93*4882a593Smuzhiyun #define IMX6SLL_CLK_AHB 80 94*4882a593Smuzhiyun #define IMX6SLL_CLK_IPG 81 95*4882a593Smuzhiyun #define IMX6SLL_CLK_PERCLK 82 96*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC1_PODF 83 97*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC2_PODF 84 98*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC3_PODF 85 99*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI1_PRED 86 100*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI2_PRED 87 101*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI3_PRED 88 102*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI1_PODF 89 103*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI2_PODF 90 104*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI3_PODF 91 105*4882a593Smuzhiyun #define IMX6SLL_CLK_PXP_PODF 92 106*4882a593Smuzhiyun #define IMX6SLL_CLK_LCDIF_PRED 93 107*4882a593Smuzhiyun #define IMX6SLL_CLK_LCDIF_PODF 94 108*4882a593Smuzhiyun #define IMX6SLL_CLK_EPDC_SEL 95 109*4882a593Smuzhiyun #define IMX6SLL_CLK_EPDC_PODF 96 110*4882a593Smuzhiyun #define IMX6SLL_CLK_SPDIF_PRED 97 111*4882a593Smuzhiyun #define IMX6SLL_CLK_SPDIF_PODF 98 112*4882a593Smuzhiyun #define IMX6SLL_CLK_ECSPI_PODF 99 113*4882a593Smuzhiyun #define IMX6SLL_CLK_UART_PODF 100 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* CCGR 0 */ 116*4882a593Smuzhiyun #define IMX6SLL_CLK_AIPSTZ1 101 117*4882a593Smuzhiyun #define IMX6SLL_CLK_AIPSTZ2 102 118*4882a593Smuzhiyun #define IMX6SLL_CLK_DCP 103 119*4882a593Smuzhiyun #define IMX6SLL_CLK_UART2_IPG 104 120*4882a593Smuzhiyun #define IMX6SLL_CLK_UART2_SERIAL 105 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* CCGR 1 */ 123*4882a593Smuzhiyun #define IMX6SLL_CLK_ECSPI1 106 124*4882a593Smuzhiyun #define IMX6SLL_CLK_ECSPI2 107 125*4882a593Smuzhiyun #define IMX6SLL_CLK_ECSPI3 108 126*4882a593Smuzhiyun #define IMX6SLL_CLK_ECSPI4 109 127*4882a593Smuzhiyun #define IMX6SLL_CLK_UART3_IPG 110 128*4882a593Smuzhiyun #define IMX6SLL_CLK_UART3_SERIAL 111 129*4882a593Smuzhiyun #define IMX6SLL_CLK_UART4_IPG 112 130*4882a593Smuzhiyun #define IMX6SLL_CLK_UART4_SERIAL 113 131*4882a593Smuzhiyun #define IMX6SLL_CLK_EPIT1 114 132*4882a593Smuzhiyun #define IMX6SLL_CLK_EPIT2 115 133*4882a593Smuzhiyun #define IMX6SLL_CLK_GPT_BUS 116 134*4882a593Smuzhiyun #define IMX6SLL_CLK_GPT_SERIAL 117 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* CCGR2 */ 137*4882a593Smuzhiyun #define IMX6SLL_CLK_CSI 118 138*4882a593Smuzhiyun #define IMX6SLL_CLK_I2C1 119 139*4882a593Smuzhiyun #define IMX6SLL_CLK_I2C2 120 140*4882a593Smuzhiyun #define IMX6SLL_CLK_I2C3 121 141*4882a593Smuzhiyun #define IMX6SLL_CLK_OCOTP 122 142*4882a593Smuzhiyun #define IMX6SLL_CLK_LCDIF_APB 123 143*4882a593Smuzhiyun #define IMX6SLL_CLK_PXP 124 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* CCGR3 */ 146*4882a593Smuzhiyun #define IMX6SLL_CLK_UART5_IPG 125 147*4882a593Smuzhiyun #define IMX6SLL_CLK_UART5_SERIAL 126 148*4882a593Smuzhiyun #define IMX6SLL_CLK_EPDC_AXI 127 149*4882a593Smuzhiyun #define IMX6SLL_CLK_EPDC_PIX 128 150*4882a593Smuzhiyun #define IMX6SLL_CLK_LCDIF_PIX 129 151*4882a593Smuzhiyun #define IMX6SLL_CLK_WDOG1 130 152*4882a593Smuzhiyun #define IMX6SLL_CLK_MMDC_P0_FAST 131 153*4882a593Smuzhiyun #define IMX6SLL_CLK_MMDC_P0_IPG 132 154*4882a593Smuzhiyun #define IMX6SLL_CLK_OCRAM 133 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* CCGR4 */ 157*4882a593Smuzhiyun #define IMX6SLL_CLK_PWM1 134 158*4882a593Smuzhiyun #define IMX6SLL_CLK_PWM2 135 159*4882a593Smuzhiyun #define IMX6SLL_CLK_PWM3 136 160*4882a593Smuzhiyun #define IMX6SLL_CLK_PWM4 137 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun /* CCGR 5 */ 163*4882a593Smuzhiyun #define IMX6SLL_CLK_ROM 138 164*4882a593Smuzhiyun #define IMX6SLL_CLK_SDMA 139 165*4882a593Smuzhiyun #define IMX6SLL_CLK_KPP 140 166*4882a593Smuzhiyun #define IMX6SLL_CLK_WDOG2 141 167*4882a593Smuzhiyun #define IMX6SLL_CLK_SPBA 142 168*4882a593Smuzhiyun #define IMX6SLL_CLK_SPDIF 143 169*4882a593Smuzhiyun #define IMX6SLL_CLK_SPDIF_GCLK 144 170*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI1 145 171*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI1_IPG 146 172*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI2 147 173*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI2_IPG 148 174*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI3 149 175*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI3_IPG 150 176*4882a593Smuzhiyun #define IMX6SLL_CLK_UART1_IPG 151 177*4882a593Smuzhiyun #define IMX6SLL_CLK_UART1_SERIAL 152 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* CCGR 6 */ 180*4882a593Smuzhiyun #define IMX6SLL_CLK_USBOH3 153 181*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC1 154 182*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC2 155 183*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC3 156 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #define IMX6SLL_CLK_IPP_DI0 157 186*4882a593Smuzhiyun #define IMX6SLL_CLK_IPP_DI1 158 187*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI0_SEL 159 188*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160 189*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI0_DIV_7 161 190*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162 191*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI0 163 192*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI1_SEL 164 193*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165 194*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI1_DIV_7 166 195*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167 196*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI1 168 197*4882a593Smuzhiyun #define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169 198*4882a593Smuzhiyun #define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 199*4882a593Smuzhiyun #define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 200*4882a593Smuzhiyun #define IMX6SLL_CLK_EXTERN_AUDIO 172 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun #define IMX6SLL_CLK_END 173 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ 205