1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 6*4882a593Smuzhiyun * published by the Free Software Foundation. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX6SL_H 11*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX6SL_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define IMX6SL_CLK_DUMMY 0 14*4882a593Smuzhiyun #define IMX6SL_CLK_CKIL 1 15*4882a593Smuzhiyun #define IMX6SL_CLK_OSC 2 16*4882a593Smuzhiyun #define IMX6SL_CLK_PLL1_SYS 3 17*4882a593Smuzhiyun #define IMX6SL_CLK_PLL2_BUS 4 18*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_USB_OTG 5 19*4882a593Smuzhiyun #define IMX6SL_CLK_PLL4_AUDIO 6 20*4882a593Smuzhiyun #define IMX6SL_CLK_PLL5_VIDEO 7 21*4882a593Smuzhiyun #define IMX6SL_CLK_PLL6_ENET 8 22*4882a593Smuzhiyun #define IMX6SL_CLK_PLL7_USB_HOST 9 23*4882a593Smuzhiyun #define IMX6SL_CLK_USBPHY1 10 24*4882a593Smuzhiyun #define IMX6SL_CLK_USBPHY2 11 25*4882a593Smuzhiyun #define IMX6SL_CLK_USBPHY1_GATE 12 26*4882a593Smuzhiyun #define IMX6SL_CLK_USBPHY2_GATE 13 27*4882a593Smuzhiyun #define IMX6SL_CLK_PLL4_POST_DIV 14 28*4882a593Smuzhiyun #define IMX6SL_CLK_PLL5_POST_DIV 15 29*4882a593Smuzhiyun #define IMX6SL_CLK_PLL5_VIDEO_DIV 16 30*4882a593Smuzhiyun #define IMX6SL_CLK_ENET_REF 17 31*4882a593Smuzhiyun #define IMX6SL_CLK_PLL2_PFD0 18 32*4882a593Smuzhiyun #define IMX6SL_CLK_PLL2_PFD1 19 33*4882a593Smuzhiyun #define IMX6SL_CLK_PLL2_PFD2 20 34*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_PFD0 21 35*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_PFD1 22 36*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_PFD2 23 37*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_PFD3 24 38*4882a593Smuzhiyun #define IMX6SL_CLK_PLL2_198M 25 39*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_120M 26 40*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_80M 27 41*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_60M 28 42*4882a593Smuzhiyun #define IMX6SL_CLK_STEP 29 43*4882a593Smuzhiyun #define IMX6SL_CLK_PLL1_SW 30 44*4882a593Smuzhiyun #define IMX6SL_CLK_OCRAM_ALT_SEL 31 45*4882a593Smuzhiyun #define IMX6SL_CLK_OCRAM_SEL 32 46*4882a593Smuzhiyun #define IMX6SL_CLK_PRE_PERIPH2_SEL 33 47*4882a593Smuzhiyun #define IMX6SL_CLK_PRE_PERIPH_SEL 34 48*4882a593Smuzhiyun #define IMX6SL_CLK_PERIPH2_CLK2_SEL 35 49*4882a593Smuzhiyun #define IMX6SL_CLK_PERIPH_CLK2_SEL 36 50*4882a593Smuzhiyun #define IMX6SL_CLK_CSI_SEL 37 51*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_AXI_SEL 38 52*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC1_SEL 39 53*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC2_SEL 40 54*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC3_SEL 41 55*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC4_SEL 42 56*4882a593Smuzhiyun #define IMX6SL_CLK_SSI1_SEL 43 57*4882a593Smuzhiyun #define IMX6SL_CLK_SSI2_SEL 44 58*4882a593Smuzhiyun #define IMX6SL_CLK_SSI3_SEL 45 59*4882a593Smuzhiyun #define IMX6SL_CLK_PERCLK_SEL 46 60*4882a593Smuzhiyun #define IMX6SL_CLK_PXP_AXI_SEL 47 61*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_AXI_SEL 48 62*4882a593Smuzhiyun #define IMX6SL_CLK_GPU2D_OVG_SEL 49 63*4882a593Smuzhiyun #define IMX6SL_CLK_GPU2D_SEL 50 64*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_PIX_SEL 51 65*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_PIX_SEL 52 66*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF0_SEL 53 67*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF1_SEL 54 68*4882a593Smuzhiyun #define IMX6SL_CLK_EXTERN_AUDIO_SEL 55 69*4882a593Smuzhiyun #define IMX6SL_CLK_ECSPI_SEL 56 70*4882a593Smuzhiyun #define IMX6SL_CLK_UART_SEL 57 71*4882a593Smuzhiyun #define IMX6SL_CLK_PERIPH 58 72*4882a593Smuzhiyun #define IMX6SL_CLK_PERIPH2 59 73*4882a593Smuzhiyun #define IMX6SL_CLK_OCRAM_PODF 60 74*4882a593Smuzhiyun #define IMX6SL_CLK_PERIPH_CLK2_PODF 61 75*4882a593Smuzhiyun #define IMX6SL_CLK_PERIPH2_CLK2_PODF 62 76*4882a593Smuzhiyun #define IMX6SL_CLK_IPG 63 77*4882a593Smuzhiyun #define IMX6SL_CLK_CSI_PODF 64 78*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_AXI_PODF 65 79*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC1_PODF 66 80*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC2_PODF 67 81*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC3_PODF 68 82*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC4_PODF 69 83*4882a593Smuzhiyun #define IMX6SL_CLK_SSI1_PRED 70 84*4882a593Smuzhiyun #define IMX6SL_CLK_SSI1_PODF 71 85*4882a593Smuzhiyun #define IMX6SL_CLK_SSI2_PRED 72 86*4882a593Smuzhiyun #define IMX6SL_CLK_SSI2_PODF 73 87*4882a593Smuzhiyun #define IMX6SL_CLK_SSI3_PRED 74 88*4882a593Smuzhiyun #define IMX6SL_CLK_SSI3_PODF 75 89*4882a593Smuzhiyun #define IMX6SL_CLK_PERCLK 76 90*4882a593Smuzhiyun #define IMX6SL_CLK_PXP_AXI_PODF 77 91*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_AXI_PODF 78 92*4882a593Smuzhiyun #define IMX6SL_CLK_GPU2D_OVG_PODF 79 93*4882a593Smuzhiyun #define IMX6SL_CLK_GPU2D_PODF 80 94*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_PIX_PRED 81 95*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_PIX_PRED 82 96*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_PIX_PODF 83 97*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_PIX_PODF 84 98*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF0_PRED 85 99*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF0_PODF 86 100*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF1_PRED 87 101*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF1_PODF 88 102*4882a593Smuzhiyun #define IMX6SL_CLK_EXTERN_AUDIO_PRED 89 103*4882a593Smuzhiyun #define IMX6SL_CLK_EXTERN_AUDIO_PODF 90 104*4882a593Smuzhiyun #define IMX6SL_CLK_ECSPI_ROOT 91 105*4882a593Smuzhiyun #define IMX6SL_CLK_UART_ROOT 92 106*4882a593Smuzhiyun #define IMX6SL_CLK_AHB 93 107*4882a593Smuzhiyun #define IMX6SL_CLK_MMDC_ROOT 94 108*4882a593Smuzhiyun #define IMX6SL_CLK_ARM 95 109*4882a593Smuzhiyun #define IMX6SL_CLK_ECSPI1 96 110*4882a593Smuzhiyun #define IMX6SL_CLK_ECSPI2 97 111*4882a593Smuzhiyun #define IMX6SL_CLK_ECSPI3 98 112*4882a593Smuzhiyun #define IMX6SL_CLK_ECSPI4 99 113*4882a593Smuzhiyun #define IMX6SL_CLK_EPIT1 100 114*4882a593Smuzhiyun #define IMX6SL_CLK_EPIT2 101 115*4882a593Smuzhiyun #define IMX6SL_CLK_EXTERN_AUDIO 102 116*4882a593Smuzhiyun #define IMX6SL_CLK_GPT 103 117*4882a593Smuzhiyun #define IMX6SL_CLK_GPT_SERIAL 104 118*4882a593Smuzhiyun #define IMX6SL_CLK_GPU2D_OVG 105 119*4882a593Smuzhiyun #define IMX6SL_CLK_I2C1 106 120*4882a593Smuzhiyun #define IMX6SL_CLK_I2C2 107 121*4882a593Smuzhiyun #define IMX6SL_CLK_I2C3 108 122*4882a593Smuzhiyun #define IMX6SL_CLK_OCOTP 109 123*4882a593Smuzhiyun #define IMX6SL_CLK_CSI 110 124*4882a593Smuzhiyun #define IMX6SL_CLK_PXP_AXI 111 125*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_AXI 112 126*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_AXI 113 127*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_PIX 114 128*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_PIX 115 129*4882a593Smuzhiyun #define IMX6SL_CLK_OCRAM 116 130*4882a593Smuzhiyun #define IMX6SL_CLK_PWM1 117 131*4882a593Smuzhiyun #define IMX6SL_CLK_PWM2 118 132*4882a593Smuzhiyun #define IMX6SL_CLK_PWM3 119 133*4882a593Smuzhiyun #define IMX6SL_CLK_PWM4 120 134*4882a593Smuzhiyun #define IMX6SL_CLK_SDMA 121 135*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF 122 136*4882a593Smuzhiyun #define IMX6SL_CLK_SSI1 123 137*4882a593Smuzhiyun #define IMX6SL_CLK_SSI2 124 138*4882a593Smuzhiyun #define IMX6SL_CLK_SSI3 125 139*4882a593Smuzhiyun #define IMX6SL_CLK_UART 126 140*4882a593Smuzhiyun #define IMX6SL_CLK_UART_SERIAL 127 141*4882a593Smuzhiyun #define IMX6SL_CLK_USBOH3 128 142*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC1 129 143*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC2 130 144*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC3 131 145*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC4 132 146*4882a593Smuzhiyun #define IMX6SL_CLK_PLL4_AUDIO_DIV 133 147*4882a593Smuzhiyun #define IMX6SL_CLK_SPBA 134 148*4882a593Smuzhiyun #define IMX6SL_CLK_ENET 135 149*4882a593Smuzhiyun #define IMX6SL_CLK_LVDS1_SEL 136 150*4882a593Smuzhiyun #define IMX6SL_CLK_LVDS1_OUT 137 151*4882a593Smuzhiyun #define IMX6SL_CLK_LVDS1_IN 138 152*4882a593Smuzhiyun #define IMX6SL_CLK_ANACLK1 139 153*4882a593Smuzhiyun #define IMX6SL_PLL1_BYPASS_SRC 140 154*4882a593Smuzhiyun #define IMX6SL_PLL2_BYPASS_SRC 141 155*4882a593Smuzhiyun #define IMX6SL_PLL3_BYPASS_SRC 142 156*4882a593Smuzhiyun #define IMX6SL_PLL4_BYPASS_SRC 143 157*4882a593Smuzhiyun #define IMX6SL_PLL5_BYPASS_SRC 144 158*4882a593Smuzhiyun #define IMX6SL_PLL6_BYPASS_SRC 145 159*4882a593Smuzhiyun #define IMX6SL_PLL7_BYPASS_SRC 146 160*4882a593Smuzhiyun #define IMX6SL_CLK_PLL1 147 161*4882a593Smuzhiyun #define IMX6SL_CLK_PLL2 148 162*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3 149 163*4882a593Smuzhiyun #define IMX6SL_CLK_PLL4 150 164*4882a593Smuzhiyun #define IMX6SL_CLK_PLL5 151 165*4882a593Smuzhiyun #define IMX6SL_CLK_PLL6 152 166*4882a593Smuzhiyun #define IMX6SL_CLK_PLL7 153 167*4882a593Smuzhiyun #define IMX6SL_PLL1_BYPASS 154 168*4882a593Smuzhiyun #define IMX6SL_PLL2_BYPASS 155 169*4882a593Smuzhiyun #define IMX6SL_PLL3_BYPASS 156 170*4882a593Smuzhiyun #define IMX6SL_PLL4_BYPASS 157 171*4882a593Smuzhiyun #define IMX6SL_PLL5_BYPASS 158 172*4882a593Smuzhiyun #define IMX6SL_PLL6_BYPASS 159 173*4882a593Smuzhiyun #define IMX6SL_PLL7_BYPASS 160 174*4882a593Smuzhiyun #define IMX6SL_CLK_SSI1_IPG 161 175*4882a593Smuzhiyun #define IMX6SL_CLK_SSI2_IPG 162 176*4882a593Smuzhiyun #define IMX6SL_CLK_SSI3_IPG 163 177*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF_GCLK 164 178*4882a593Smuzhiyun #define IMX6SL_CLK_END 165 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ 181