1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2015 Hisilicon Limited. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Author: Bintian Wang <bintian.wang@huawei.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 7*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 8*4882a593Smuzhiyun * published by the Free Software Foundation. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_HI6220_H 12*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_HI6220_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* clk in Hi6220 AO (always on) controller */ 15*4882a593Smuzhiyun #define HI6220_NONE_CLOCK 0 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* fixed rate clocks */ 18*4882a593Smuzhiyun #define HI6220_REF32K 1 19*4882a593Smuzhiyun #define HI6220_CLK_TCXO 2 20*4882a593Smuzhiyun #define HI6220_MMC1_PAD 3 21*4882a593Smuzhiyun #define HI6220_MMC2_PAD 4 22*4882a593Smuzhiyun #define HI6220_MMC0_PAD 5 23*4882a593Smuzhiyun #define HI6220_PLL_BBP 6 24*4882a593Smuzhiyun #define HI6220_PLL_GPU 7 25*4882a593Smuzhiyun #define HI6220_PLL1_DDR 8 26*4882a593Smuzhiyun #define HI6220_PLL_SYS 9 27*4882a593Smuzhiyun #define HI6220_PLL_SYS_MEDIA 10 28*4882a593Smuzhiyun #define HI6220_DDR_SRC 11 29*4882a593Smuzhiyun #define HI6220_PLL_MEDIA 12 30*4882a593Smuzhiyun #define HI6220_PLL_DDR 13 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* fixed factor clocks */ 33*4882a593Smuzhiyun #define HI6220_300M 14 34*4882a593Smuzhiyun #define HI6220_150M 15 35*4882a593Smuzhiyun #define HI6220_PICOPHY_SRC 16 36*4882a593Smuzhiyun #define HI6220_MMC0_SRC_SEL 17 37*4882a593Smuzhiyun #define HI6220_MMC1_SRC_SEL 18 38*4882a593Smuzhiyun #define HI6220_MMC2_SRC_SEL 19 39*4882a593Smuzhiyun #define HI6220_VPU_CODEC 20 40*4882a593Smuzhiyun #define HI6220_MMC0_SMP 21 41*4882a593Smuzhiyun #define HI6220_MMC1_SMP 22 42*4882a593Smuzhiyun #define HI6220_MMC2_SMP 23 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* gate clocks */ 45*4882a593Smuzhiyun #define HI6220_WDT0_PCLK 24 46*4882a593Smuzhiyun #define HI6220_WDT1_PCLK 25 47*4882a593Smuzhiyun #define HI6220_WDT2_PCLK 26 48*4882a593Smuzhiyun #define HI6220_TIMER0_PCLK 27 49*4882a593Smuzhiyun #define HI6220_TIMER1_PCLK 28 50*4882a593Smuzhiyun #define HI6220_TIMER2_PCLK 29 51*4882a593Smuzhiyun #define HI6220_TIMER3_PCLK 30 52*4882a593Smuzhiyun #define HI6220_TIMER4_PCLK 31 53*4882a593Smuzhiyun #define HI6220_TIMER5_PCLK 32 54*4882a593Smuzhiyun #define HI6220_TIMER6_PCLK 33 55*4882a593Smuzhiyun #define HI6220_TIMER7_PCLK 34 56*4882a593Smuzhiyun #define HI6220_TIMER8_PCLK 35 57*4882a593Smuzhiyun #define HI6220_UART0_PCLK 36 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define HI6220_AO_NR_CLKS 37 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* clk in Hi6220 systrl */ 62*4882a593Smuzhiyun /* gate clock */ 63*4882a593Smuzhiyun #define HI6220_MMC0_CLK 1 64*4882a593Smuzhiyun #define HI6220_MMC0_CIUCLK 2 65*4882a593Smuzhiyun #define HI6220_MMC1_CLK 3 66*4882a593Smuzhiyun #define HI6220_MMC1_CIUCLK 4 67*4882a593Smuzhiyun #define HI6220_MMC2_CLK 5 68*4882a593Smuzhiyun #define HI6220_MMC2_CIUCLK 6 69*4882a593Smuzhiyun #define HI6220_USBOTG_HCLK 7 70*4882a593Smuzhiyun #define HI6220_CLK_PICOPHY 8 71*4882a593Smuzhiyun #define HI6220_HIFI 9 72*4882a593Smuzhiyun #define HI6220_DACODEC_PCLK 10 73*4882a593Smuzhiyun #define HI6220_EDMAC_ACLK 11 74*4882a593Smuzhiyun #define HI6220_CS_ATB 12 75*4882a593Smuzhiyun #define HI6220_I2C0_CLK 13 76*4882a593Smuzhiyun #define HI6220_I2C1_CLK 14 77*4882a593Smuzhiyun #define HI6220_I2C2_CLK 15 78*4882a593Smuzhiyun #define HI6220_I2C3_CLK 16 79*4882a593Smuzhiyun #define HI6220_UART1_PCLK 17 80*4882a593Smuzhiyun #define HI6220_UART2_PCLK 18 81*4882a593Smuzhiyun #define HI6220_UART3_PCLK 19 82*4882a593Smuzhiyun #define HI6220_UART4_PCLK 20 83*4882a593Smuzhiyun #define HI6220_SPI_CLK 21 84*4882a593Smuzhiyun #define HI6220_TSENSOR_CLK 22 85*4882a593Smuzhiyun #define HI6220_MMU_CLK 23 86*4882a593Smuzhiyun #define HI6220_HIFI_SEL 24 87*4882a593Smuzhiyun #define HI6220_MMC0_SYSPLL 25 88*4882a593Smuzhiyun #define HI6220_MMC1_SYSPLL 26 89*4882a593Smuzhiyun #define HI6220_MMC2_SYSPLL 27 90*4882a593Smuzhiyun #define HI6220_MMC0_SEL 28 91*4882a593Smuzhiyun #define HI6220_MMC1_SEL 29 92*4882a593Smuzhiyun #define HI6220_BBPPLL_SEL 30 93*4882a593Smuzhiyun #define HI6220_MEDIA_PLL_SRC 31 94*4882a593Smuzhiyun #define HI6220_MMC2_SEL 32 95*4882a593Smuzhiyun #define HI6220_CS_ATB_SYSPLL 33 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* mux clocks */ 98*4882a593Smuzhiyun #define HI6220_MMC0_SRC 34 99*4882a593Smuzhiyun #define HI6220_MMC0_SMP_IN 35 100*4882a593Smuzhiyun #define HI6220_MMC1_SRC 36 101*4882a593Smuzhiyun #define HI6220_MMC1_SMP_IN 37 102*4882a593Smuzhiyun #define HI6220_MMC2_SRC 38 103*4882a593Smuzhiyun #define HI6220_MMC2_SMP_IN 39 104*4882a593Smuzhiyun #define HI6220_HIFI_SRC 40 105*4882a593Smuzhiyun #define HI6220_UART1_SRC 41 106*4882a593Smuzhiyun #define HI6220_UART2_SRC 42 107*4882a593Smuzhiyun #define HI6220_UART3_SRC 43 108*4882a593Smuzhiyun #define HI6220_UART4_SRC 44 109*4882a593Smuzhiyun #define HI6220_MMC0_MUX0 45 110*4882a593Smuzhiyun #define HI6220_MMC1_MUX0 46 111*4882a593Smuzhiyun #define HI6220_MMC2_MUX0 47 112*4882a593Smuzhiyun #define HI6220_MMC0_MUX1 48 113*4882a593Smuzhiyun #define HI6220_MMC1_MUX1 49 114*4882a593Smuzhiyun #define HI6220_MMC2_MUX1 50 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* divider clocks */ 117*4882a593Smuzhiyun #define HI6220_CLK_BUS 51 118*4882a593Smuzhiyun #define HI6220_MMC0_DIV 52 119*4882a593Smuzhiyun #define HI6220_MMC1_DIV 53 120*4882a593Smuzhiyun #define HI6220_MMC2_DIV 54 121*4882a593Smuzhiyun #define HI6220_HIFI_DIV 55 122*4882a593Smuzhiyun #define HI6220_BBPPLL0_DIV 56 123*4882a593Smuzhiyun #define HI6220_CS_DAPB 57 124*4882a593Smuzhiyun #define HI6220_CS_ATB_DIV 58 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define HI6220_SYS_NR_CLKS 59 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* clk in Hi6220 media controller */ 129*4882a593Smuzhiyun /* gate clocks */ 130*4882a593Smuzhiyun #define HI6220_DSI_PCLK 1 131*4882a593Smuzhiyun #define HI6220_G3D_PCLK 2 132*4882a593Smuzhiyun #define HI6220_ACLK_CODEC_VPU 3 133*4882a593Smuzhiyun #define HI6220_ISP_SCLK 4 134*4882a593Smuzhiyun #define HI6220_ADE_CORE 5 135*4882a593Smuzhiyun #define HI6220_MED_MMU 6 136*4882a593Smuzhiyun #define HI6220_CFG_CSI4PHY 7 137*4882a593Smuzhiyun #define HI6220_CFG_CSI2PHY 8 138*4882a593Smuzhiyun #define HI6220_ISP_SCLK_GATE 9 139*4882a593Smuzhiyun #define HI6220_ISP_SCLK_GATE1 10 140*4882a593Smuzhiyun #define HI6220_ADE_CORE_GATE 11 141*4882a593Smuzhiyun #define HI6220_CODEC_VPU_GATE 12 142*4882a593Smuzhiyun #define HI6220_MED_SYSPLL 13 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* mux clocks */ 145*4882a593Smuzhiyun #define HI6220_1440_1200 14 146*4882a593Smuzhiyun #define HI6220_1000_1200 15 147*4882a593Smuzhiyun #define HI6220_1000_1440 16 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun /* divider clocks */ 150*4882a593Smuzhiyun #define HI6220_CODEC_JPEG 17 151*4882a593Smuzhiyun #define HI6220_ISP_SCLK_SRC 18 152*4882a593Smuzhiyun #define HI6220_ISP_SCLK1 19 153*4882a593Smuzhiyun #define HI6220_ADE_CORE_SRC 20 154*4882a593Smuzhiyun #define HI6220_ADE_PIX_SRC 21 155*4882a593Smuzhiyun #define HI6220_G3D_CLK 22 156*4882a593Smuzhiyun #define HI6220_CODEC_VPU_SRC 23 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define HI6220_MEDIA_NR_CLKS 24 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* clk in Hi6220 power controller */ 161*4882a593Smuzhiyun /* gate clocks */ 162*4882a593Smuzhiyun #define HI6220_PLL_GPU_GATE 1 163*4882a593Smuzhiyun #define HI6220_PLL1_DDR_GATE 2 164*4882a593Smuzhiyun #define HI6220_PLL_DDR_GATE 3 165*4882a593Smuzhiyun #define HI6220_PLL_MEDIA_GATE 4 166*4882a593Smuzhiyun #define HI6220_PLL0_BBP_GATE 5 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* divider clocks */ 169*4882a593Smuzhiyun #define HI6220_DDRC_SRC 6 170*4882a593Smuzhiyun #define HI6220_DDRC_AXI1 7 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #define HI6220_POWER_NR_CLKS 8 173*4882a593Smuzhiyun #endif 174