1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_BCM6328_H 10*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_BCM6328_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define BCM6328_CLK_PHYMIPS 0 13*4882a593Smuzhiyun #define BCM6328_CLK_ADSL_QPROC 1 14*4882a593Smuzhiyun #define BCM6328_CLK_ADSL_AFE 2 15*4882a593Smuzhiyun #define BCM6328_CLK_ADSL 3 16*4882a593Smuzhiyun #define BCM6328_CLK_MIPS 4 17*4882a593Smuzhiyun #define BCM6328_CLK_SAR 5 18*4882a593Smuzhiyun #define BCM6328_CLK_PCM 6 19*4882a593Smuzhiyun #define BCM6328_CLK_USBD 7 20*4882a593Smuzhiyun #define BCM6328_CLK_USBH 8 21*4882a593Smuzhiyun #define BCM6328_CLK_HSSPI 9 22*4882a593Smuzhiyun #define BCM6328_CLK_PCIE 10 23*4882a593Smuzhiyun #define BCM6328_CLK_ROBOSW 11 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_BCM6328_H */ 26