xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/include/dt-bindings/clk/ti-dra7-atl.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * This header provides constants for DRA7 ATL (Audio Tracking Logic)
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * The constants defined in this header are used in dts files
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2013 Texas Instruments, Inc.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Peter Ujfalusi <peter.ujfalusi@ti.com>
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
11*4882a593Smuzhiyun  * it under the terms of the GNU General Public License version 2 as
12*4882a593Smuzhiyun  * published by the Free Software Foundation.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
15*4882a593Smuzhiyun  * kind, whether express or implied; without even the implied warranty
16*4882a593Smuzhiyun  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17*4882a593Smuzhiyun  * GNU General Public License for more details.
18*4882a593Smuzhiyun  */
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_DRA7_ATL_H
21*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_DRA7_ATL_H
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define DRA7_ATL_WS_MCASP1_FSR		0
24*4882a593Smuzhiyun #define DRA7_ATL_WS_MCASP1_FSX		1
25*4882a593Smuzhiyun #define DRA7_ATL_WS_MCASP2_FSR		2
26*4882a593Smuzhiyun #define DRA7_ATL_WS_MCASP2_FSX		3
27*4882a593Smuzhiyun #define DRA7_ATL_WS_MCASP3_FSX		4
28*4882a593Smuzhiyun #define DRA7_ATL_WS_MCASP4_FSX		5
29*4882a593Smuzhiyun #define DRA7_ATL_WS_MCASP5_FSX		6
30*4882a593Smuzhiyun #define DRA7_ATL_WS_MCASP6_FSX		7
31*4882a593Smuzhiyun #define DRA7_ATL_WS_MCASP7_FSX		8
32*4882a593Smuzhiyun #define DRA7_ATL_WS_MCASP8_FSX		9
33*4882a593Smuzhiyun #define DRA7_ATL_WS_MCASP8_AHCLKX	10
34*4882a593Smuzhiyun #define DRA7_ATL_WS_XREF_CLK3		11
35*4882a593Smuzhiyun #define DRA7_ATL_WS_XREF_CLK0		12
36*4882a593Smuzhiyun #define DRA7_ATL_WS_XREF_CLK1		13
37*4882a593Smuzhiyun #define DRA7_ATL_WS_XREF_CLK2		14
38*4882a593Smuzhiyun #define DRA7_ATL_WS_OSC1_X1		15
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #endif
41