xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/imx7d-sdb.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright 2017 NXP
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include "imx7d.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	model = "Freescale i.MX7 SabreSD Board";
13*4882a593Smuzhiyun	compatible = "fsl,imx7d-sdb", "fsl,imx7d";
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	memory {
16*4882a593Smuzhiyun		reg = <0x80000000 0x80000000>;
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	spi4 {
20*4882a593Smuzhiyun		compatible = "spi-gpio";
21*4882a593Smuzhiyun		pinctrl-names = "default";
22*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_spi1>;
23*4882a593Smuzhiyun		status = "okay";
24*4882a593Smuzhiyun		gpio-sck = <&gpio1 13 0>;
25*4882a593Smuzhiyun		gpio-mosi = <&gpio1 9 0>;
26*4882a593Smuzhiyun		cs-gpios = <&gpio1 12 0>;
27*4882a593Smuzhiyun		num-chipselects = <1>;
28*4882a593Smuzhiyun		#address-cells = <1>;
29*4882a593Smuzhiyun		#size-cells = <0>;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun		gpio_spi: gpio_spi@0 {
32*4882a593Smuzhiyun			compatible = "fairchild,74hc595";
33*4882a593Smuzhiyun			gpio-controller;
34*4882a593Smuzhiyun			#gpio-cells = <2>;
35*4882a593Smuzhiyun			reg = <0>;
36*4882a593Smuzhiyun			registers-number = <1>;
37*4882a593Smuzhiyun			registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/
38*4882a593Smuzhiyun			spi-max-frequency = <100000>;
39*4882a593Smuzhiyun		};
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	regulators {
43*4882a593Smuzhiyun		compatible = "simple-bus";
44*4882a593Smuzhiyun		#address-cells = <1>;
45*4882a593Smuzhiyun		#size-cells = <0>;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun		reg_usb_otg1_vbus: regulator@0 {
48*4882a593Smuzhiyun			compatible = "regulator-fixed";
49*4882a593Smuzhiyun			reg = <0>;
50*4882a593Smuzhiyun			regulator-name = "usb_otg1_vbus";
51*4882a593Smuzhiyun			regulator-min-microvolt = <5000000>;
52*4882a593Smuzhiyun			regulator-max-microvolt = <5000000>;
53*4882a593Smuzhiyun			gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
54*4882a593Smuzhiyun			enable-active-high;
55*4882a593Smuzhiyun		};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun		reg_usb_otg2_vbus: regulator@1 {
58*4882a593Smuzhiyun			compatible = "regulator-fixed";
59*4882a593Smuzhiyun			reg = <1>;
60*4882a593Smuzhiyun			regulator-name = "usb_otg2_vbus";
61*4882a593Smuzhiyun			regulator-min-microvolt = <5000000>;
62*4882a593Smuzhiyun			regulator-max-microvolt = <5000000>;
63*4882a593Smuzhiyun			gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
64*4882a593Smuzhiyun			enable-active-high;
65*4882a593Smuzhiyun		};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun		reg_sd1_vmmc: regulator@3 {
68*4882a593Smuzhiyun			compatible = "regulator-fixed";
69*4882a593Smuzhiyun			regulator-name = "VDD_SD1";
70*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
71*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
72*4882a593Smuzhiyun			gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
73*4882a593Smuzhiyun			startup-delay-us = <200000>;
74*4882a593Smuzhiyun			enable-active-high;
75*4882a593Smuzhiyun		};
76*4882a593Smuzhiyun	};
77*4882a593Smuzhiyun};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun&iomuxc {
80*4882a593Smuzhiyun	imx7d-sdb {
81*4882a593Smuzhiyun		pinctrl_spi1: spi1grp {
82*4882a593Smuzhiyun			fsl,pins = <
83*4882a593Smuzhiyun				MX7D_PAD_GPIO1_IO09__GPIO1_IO9	0x59
84*4882a593Smuzhiyun				MX7D_PAD_GPIO1_IO12__GPIO1_IO12	0x59
85*4882a593Smuzhiyun				MX7D_PAD_GPIO1_IO13__GPIO1_IO13	0x59
86*4882a593Smuzhiyun			>;
87*4882a593Smuzhiyun		};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun		pinctrl_i2c1: i2c1grp {
90*4882a593Smuzhiyun			fsl,pins = <
91*4882a593Smuzhiyun				MX7D_PAD_I2C1_SDA__I2C1_SDA	0x4000007f
92*4882a593Smuzhiyun				MX7D_PAD_I2C1_SCL__I2C1_SCL	0x4000007f
93*4882a593Smuzhiyun			>;
94*4882a593Smuzhiyun		};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun		pinctrl_i2c2: i2c2grp {
97*4882a593Smuzhiyun			fsl,pins = <
98*4882a593Smuzhiyun				MX7D_PAD_I2C2_SDA__I2C2_SDA	0x4000007f
99*4882a593Smuzhiyun				MX7D_PAD_I2C2_SCL__I2C2_SCL	0x4000007f
100*4882a593Smuzhiyun			>;
101*4882a593Smuzhiyun		};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun		pinctrl_i2c3: i2c3grp {
104*4882a593Smuzhiyun			fsl,pins = <
105*4882a593Smuzhiyun				MX7D_PAD_I2C3_SDA__I2C3_SDA	0x4000007f
106*4882a593Smuzhiyun				MX7D_PAD_I2C3_SCL__I2C3_SCL	0x4000007f
107*4882a593Smuzhiyun			>;
108*4882a593Smuzhiyun		};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun		pinctrl_i2c4: i2c4grp {
111*4882a593Smuzhiyun			fsl,pins = <
112*4882a593Smuzhiyun				MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA	0x4000007f
113*4882a593Smuzhiyun				MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL	0x4000007f
114*4882a593Smuzhiyun			>;
115*4882a593Smuzhiyun		};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun		pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
118*4882a593Smuzhiyun			fsl,pins = <
119*4882a593Smuzhiyun				MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */
120*4882a593Smuzhiyun				MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* WP */
121*4882a593Smuzhiyun				MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* vmmc */
122*4882a593Smuzhiyun				MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59 /* VSELECT */
123*4882a593Smuzhiyun			>;
124*4882a593Smuzhiyun		};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun		pinctrl_usdhc1: usdhc1grp {
127*4882a593Smuzhiyun			fsl,pins = <
128*4882a593Smuzhiyun				MX7D_PAD_SD1_CMD__SD1_CMD		0x59
129*4882a593Smuzhiyun				MX7D_PAD_SD1_CLK__SD1_CLK		0x19
130*4882a593Smuzhiyun				MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
131*4882a593Smuzhiyun				MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
132*4882a593Smuzhiyun				MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
133*4882a593Smuzhiyun				MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
134*4882a593Smuzhiyun			>;
135*4882a593Smuzhiyun		};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun		pinctrl_usdhc2: usdhc2grp {
138*4882a593Smuzhiyun			fsl,pins = <
139*4882a593Smuzhiyun				MX7D_PAD_SD2_CMD__SD2_CMD       0x59
140*4882a593Smuzhiyun				MX7D_PAD_SD2_CLK__SD2_CLK       0x19
141*4882a593Smuzhiyun				MX7D_PAD_SD2_DATA0__SD2_DATA0   0x59
142*4882a593Smuzhiyun				MX7D_PAD_SD2_DATA1__SD2_DATA1   0x59
143*4882a593Smuzhiyun				MX7D_PAD_SD2_DATA2__SD2_DATA2   0x59
144*4882a593Smuzhiyun				MX7D_PAD_SD2_DATA3__SD2_DATA3   0x59
145*4882a593Smuzhiyun				MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21	0x19 /* WL_REG_ON */
146*4882a593Smuzhiyun				MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20	0x19 /* WL_HOST_WAKE */
147*4882a593Smuzhiyun			>;
148*4882a593Smuzhiyun		};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun		pinctrl_usdhc3: usdhc3grp {
151*4882a593Smuzhiyun			fsl,pins = <
152*4882a593Smuzhiyun				MX7D_PAD_SD3_CMD__SD3_CMD		0x59
153*4882a593Smuzhiyun				MX7D_PAD_SD3_CLK__SD3_CLK		0x19
154*4882a593Smuzhiyun				MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
155*4882a593Smuzhiyun				MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
156*4882a593Smuzhiyun				MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
157*4882a593Smuzhiyun				MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
158*4882a593Smuzhiyun				MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
159*4882a593Smuzhiyun				MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
160*4882a593Smuzhiyun				MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
161*4882a593Smuzhiyun				MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
162*4882a593Smuzhiyun				MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
163*4882a593Smuzhiyun			>;
164*4882a593Smuzhiyun		};
165*4882a593Smuzhiyun	};
166*4882a593Smuzhiyun};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun&i2c1 {
169*4882a593Smuzhiyun	clock-frequency = <100000>;
170*4882a593Smuzhiyun	pinctrl-names = "default";
171*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
172*4882a593Smuzhiyun	status = "okay";
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun	pmic: pfuze3000@08 {
175*4882a593Smuzhiyun		compatible = "fsl,pfuze3000";
176*4882a593Smuzhiyun		reg = <0x08>;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun		regulators {
179*4882a593Smuzhiyun			sw1a_reg: sw1a {
180*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
181*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
182*4882a593Smuzhiyun				regulator-boot-on;
183*4882a593Smuzhiyun				regulator-always-on;
184*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
185*4882a593Smuzhiyun			};
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun			/* use sw1c_reg to align with pfuze100/pfuze200 */
188*4882a593Smuzhiyun			sw1c_reg: sw1b {
189*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
190*4882a593Smuzhiyun				regulator-max-microvolt = <1475000>;
191*4882a593Smuzhiyun				regulator-boot-on;
192*4882a593Smuzhiyun				regulator-always-on;
193*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
194*4882a593Smuzhiyun			};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun			sw2_reg: sw2 {
197*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
198*4882a593Smuzhiyun				regulator-max-microvolt = <1850000>;
199*4882a593Smuzhiyun				regulator-boot-on;
200*4882a593Smuzhiyun				regulator-always-on;
201*4882a593Smuzhiyun			};
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun			sw3a_reg: sw3 {
204*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
205*4882a593Smuzhiyun				regulator-max-microvolt = <1650000>;
206*4882a593Smuzhiyun				regulator-boot-on;
207*4882a593Smuzhiyun				regulator-always-on;
208*4882a593Smuzhiyun			};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun			swbst_reg: swbst {
211*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
212*4882a593Smuzhiyun				regulator-max-microvolt = <5150000>;
213*4882a593Smuzhiyun			};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun			snvs_reg: vsnvs {
216*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
217*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
218*4882a593Smuzhiyun				regulator-boot-on;
219*4882a593Smuzhiyun				regulator-always-on;
220*4882a593Smuzhiyun			};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun			vref_reg: vrefddr {
223*4882a593Smuzhiyun				regulator-boot-on;
224*4882a593Smuzhiyun				regulator-always-on;
225*4882a593Smuzhiyun			};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun			vgen1_reg: vldo1 {
228*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
229*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
230*4882a593Smuzhiyun				regulator-always-on;
231*4882a593Smuzhiyun			};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun			vgen2_reg: vldo2 {
234*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
235*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
236*4882a593Smuzhiyun				regulator-always-on;
237*4882a593Smuzhiyun			};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun			vgen3_reg: vccsd {
240*4882a593Smuzhiyun				regulator-min-microvolt = <2850000>;
241*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
242*4882a593Smuzhiyun				regulator-always-on;
243*4882a593Smuzhiyun			};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun			vgen4_reg: v33 {
246*4882a593Smuzhiyun				regulator-min-microvolt = <2850000>;
247*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
248*4882a593Smuzhiyun				regulator-always-on;
249*4882a593Smuzhiyun			};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun			vgen5_reg: vldo3 {
252*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
253*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
254*4882a593Smuzhiyun				regulator-always-on;
255*4882a593Smuzhiyun			};
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun			vgen6_reg: vldo4 {
258*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
259*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
260*4882a593Smuzhiyun				regulator-always-on;
261*4882a593Smuzhiyun			};
262*4882a593Smuzhiyun		};
263*4882a593Smuzhiyun	};
264*4882a593Smuzhiyun};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun&i2c2 {
267*4882a593Smuzhiyun	clock-frequency = <100000>;
268*4882a593Smuzhiyun	pinctrl-names = "default";
269*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
270*4882a593Smuzhiyun	status = "okay";
271*4882a593Smuzhiyun};
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun&i2c3 {
274*4882a593Smuzhiyun	clock-frequency = <100000>;
275*4882a593Smuzhiyun	pinctrl-names = "default";
276*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
277*4882a593Smuzhiyun	status = "okay";
278*4882a593Smuzhiyun};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun&i2c4 {
281*4882a593Smuzhiyun	clock-frequency = <100000>;
282*4882a593Smuzhiyun	pinctrl-names = "default";
283*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c4>;
284*4882a593Smuzhiyun	status = "okay";
285*4882a593Smuzhiyun};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun&usdhc1 {
288*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
289*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
290*4882a593Smuzhiyun	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
291*4882a593Smuzhiyun	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
292*4882a593Smuzhiyun	vmmc-supply = <&reg_sd1_vmmc>;
293*4882a593Smuzhiyun	status = "okay";
294*4882a593Smuzhiyun};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun&usdhc2 {
297*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
298*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
299*4882a593Smuzhiyun	non-removable;
300*4882a593Smuzhiyun	status = "okay";
301*4882a593Smuzhiyun};
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun&usdhc3 {
304*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
305*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
306*4882a593Smuzhiyun	bus-width = <8>;
307*4882a593Smuzhiyun	non-removable;
308*4882a593Smuzhiyun	status = "okay";
309*4882a593Smuzhiyun};
310