1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright 2016 Toradex AG 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ or X11 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun#include "imx7d.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Toradex Colibri iMX7S/D"; 13*4882a593Smuzhiyun compatible = "toradex,imx7-colibri", "fsl,imx7"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun chosen { 16*4882a593Smuzhiyun stdout-path = &uart1; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun}; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun&i2c1 { 21*4882a593Smuzhiyun pinctrl-names = "default", "gpio"; 22*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 23*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_i2c1_gpio>; 24*4882a593Smuzhiyun sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; 25*4882a593Smuzhiyun scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 26*4882a593Smuzhiyun status = "okay"; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun rn5t567@33 { 29*4882a593Smuzhiyun compatible = "ricoh,rn5t567"; 30*4882a593Smuzhiyun reg = <0x33>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun}; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun&i2c4 { 35*4882a593Smuzhiyun pinctrl-names = "default", "gpio"; 36*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c4>; 37*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_i2c4_gpio>; 38*4882a593Smuzhiyun sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; 39*4882a593Smuzhiyun scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; 40*4882a593Smuzhiyun status = "okay"; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun&uart1 { 44*4882a593Smuzhiyun pinctrl-names = "default"; 45*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; 46*4882a593Smuzhiyun uart-has-rtscts; 47*4882a593Smuzhiyun fsl,dte-mode; 48*4882a593Smuzhiyun status = "okay"; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&iomuxc { 52*4882a593Smuzhiyun pinctrl_i2c4: i2c4-grp { 53*4882a593Smuzhiyun fsl,pins = < 54*4882a593Smuzhiyun MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f 55*4882a593Smuzhiyun MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f 56*4882a593Smuzhiyun >; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun pinctrl_i2c4_gpio: i2c4-gpio-grp { 60*4882a593Smuzhiyun fsl,pins = < 61*4882a593Smuzhiyun MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f 62*4882a593Smuzhiyun MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f 63*4882a593Smuzhiyun >; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun pinctrl_uart1: uart1-grp { 67*4882a593Smuzhiyun fsl,pins = < 68*4882a593Smuzhiyun MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 69*4882a593Smuzhiyun MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 70*4882a593Smuzhiyun MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 71*4882a593Smuzhiyun MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 72*4882a593Smuzhiyun >; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun pinctrl_uart1_ctrl1: uart1-ctrl1-grp { 76*4882a593Smuzhiyun fsl,pins = < 77*4882a593Smuzhiyun MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ 78*4882a593Smuzhiyun MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ 79*4882a593Smuzhiyun >; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun}; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun&iomuxc_lpsr { 84*4882a593Smuzhiyun pinctrl_i2c1: i2c1-grp { 85*4882a593Smuzhiyun fsl,pins = < 86*4882a593Smuzhiyun MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f 87*4882a593Smuzhiyun MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f 88*4882a593Smuzhiyun >; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun pinctrl_i2c1_gpio: i2c1-gpio-grp { 92*4882a593Smuzhiyun fsl,pins = < 93*4882a593Smuzhiyun MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f 94*4882a593Smuzhiyun MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f 95*4882a593Smuzhiyun >; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun}; 98