xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/imx6ul-opos6uldev.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright 2017 Armadeus Systems <support@armadeus.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms
5*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual
6*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a
7*4882a593Smuzhiyun * whole.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun *  a) This file is free software; you can redistribute it and/or
10*4882a593Smuzhiyun *     modify it under the terms of the GNU General Public License as
11*4882a593Smuzhiyun *     published by the Free Software Foundation; either version 2 of
12*4882a593Smuzhiyun *     the License, or (at your option) any later version.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun *     This file is distributed in the hope that it will be useful,
15*4882a593Smuzhiyun *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16*4882a593Smuzhiyun *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17*4882a593Smuzhiyun *     GNU General Public License for more details.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun *     You should have received a copy of the GNU General Public
20*4882a593Smuzhiyun *     License along with this file; if not, write to the Free
21*4882a593Smuzhiyun *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22*4882a593Smuzhiyun *     MA 02110-1301 USA
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * Or, alternatively,
25*4882a593Smuzhiyun *
26*4882a593Smuzhiyun *  b) Permission is hereby granted, free of charge, to any person
27*4882a593Smuzhiyun *     obtaining a copy of this software and associated documentation
28*4882a593Smuzhiyun *     files (the "Software"), to deal in the Software without
29*4882a593Smuzhiyun *     restriction, including without limitation the rights to use,
30*4882a593Smuzhiyun *     copy, modify, merge, publish, distribute, sublicense, and/or
31*4882a593Smuzhiyun *     sell copies of the Software, and to permit persons to whom the
32*4882a593Smuzhiyun *     Software is furnished to do so, subject to the following
33*4882a593Smuzhiyun *     conditions:
34*4882a593Smuzhiyun *
35*4882a593Smuzhiyun *     The above copyright notice and this permission notice shall be
36*4882a593Smuzhiyun *     included in all copies or substantial portions of the Software.
37*4882a593Smuzhiyun *
38*4882a593Smuzhiyun *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39*4882a593Smuzhiyun *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40*4882a593Smuzhiyun *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41*4882a593Smuzhiyun *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42*4882a593Smuzhiyun *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43*4882a593Smuzhiyun *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44*4882a593Smuzhiyun *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45*4882a593Smuzhiyun *     OTHER DEALINGS IN THE SOFTWARE.
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun/dts-v1/;
49*4882a593Smuzhiyun#include "imx6ul-opos6ul.dtsi"
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun/ {
52*4882a593Smuzhiyun	model = "Armadeus Systems OPOS6UL SoM on OPOS6ULDev board";
53*4882a593Smuzhiyun	compatible = "armadeus,opos6uldev", "armadeus,opos6ul", "fsl,imx6ul";
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun	chosen {
56*4882a593Smuzhiyun		stdout-path = &uart1;
57*4882a593Smuzhiyun	};
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun	backlight {
60*4882a593Smuzhiyun		compatible = "pwm-backlight";
61*4882a593Smuzhiyun		pwms = <&pwm3 0 191000>;
62*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
63*4882a593Smuzhiyun		default-brightness-level = <7>;
64*4882a593Smuzhiyun		power-supply = <&reg_5v>;
65*4882a593Smuzhiyun		status = "okay";
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	gpio-keys {
69*4882a593Smuzhiyun		compatible = "gpio-keys";
70*4882a593Smuzhiyun		pinctrl-names = "default";
71*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_keys>;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun		user-button {
74*4882a593Smuzhiyun			label = "User button";
75*4882a593Smuzhiyun			gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
76*4882a593Smuzhiyun			linux,code = <BTN_MISC>;
77*4882a593Smuzhiyun			wakeup-source;
78*4882a593Smuzhiyun		};
79*4882a593Smuzhiyun	};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun	leds {
82*4882a593Smuzhiyun		compatible = "gpio-leds";
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun		user-led {
85*4882a593Smuzhiyun			label = "User";
86*4882a593Smuzhiyun			pinctrl-names = "default";
87*4882a593Smuzhiyun			pinctrl-0 = <&pinctrl_led>;
88*4882a593Smuzhiyun			gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
89*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
90*4882a593Smuzhiyun		};
91*4882a593Smuzhiyun	};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun	onewire {
94*4882a593Smuzhiyun		compatible = "w1-gpio";
95*4882a593Smuzhiyun		pinctrl-names = "default";
96*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_w1>;
97*4882a593Smuzhiyun		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	reg_5v: regulator-5v {
101*4882a593Smuzhiyun		compatible = "regulator-fixed";
102*4882a593Smuzhiyun		regulator-name = "5V";
103*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
104*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
105*4882a593Smuzhiyun	};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun	reg_usbotg1_vbus: regulator-usbotg1vbus {
108*4882a593Smuzhiyun		compatible = "regulator-fixed";
109*4882a593Smuzhiyun		regulator-name = "usbotg1vbus";
110*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
111*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
112*4882a593Smuzhiyun		pinctrl-names = "default";
113*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usbotg1_vbus>;
114*4882a593Smuzhiyun		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
115*4882a593Smuzhiyun		enable-active-high;
116*4882a593Smuzhiyun	};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun	reg_usbotg2_vbus: regulator-usbotg2vbus {
119*4882a593Smuzhiyun		compatible = "regulator-fixed";
120*4882a593Smuzhiyun		regulator-name = "usbotg2vbus";
121*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
122*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
123*4882a593Smuzhiyun		pinctrl-names = "default";
124*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usbotg2_vbus>;
125*4882a593Smuzhiyun		gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
126*4882a593Smuzhiyun		enable-active-high;
127*4882a593Smuzhiyun	};
128*4882a593Smuzhiyun};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun&adc1 {
131*4882a593Smuzhiyun	vref-supply = <&reg_3v3>;
132*4882a593Smuzhiyun	status = "okay";
133*4882a593Smuzhiyun};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun&can1 {
136*4882a593Smuzhiyun	pinctrl-names = "default";
137*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan1>;
138*4882a593Smuzhiyun	xceiver-supply = <&reg_5v>;
139*4882a593Smuzhiyun	status = "okay";
140*4882a593Smuzhiyun};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun&can2 {
143*4882a593Smuzhiyun	pinctrl-names = "default";
144*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan2>;
145*4882a593Smuzhiyun	xceiver-supply = <&reg_5v>;
146*4882a593Smuzhiyun	status = "okay";
147*4882a593Smuzhiyun};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun&ecspi4 {
150*4882a593Smuzhiyun	pinctrl-names = "default";
151*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi4>;
152*4882a593Smuzhiyun	cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
153*4882a593Smuzhiyun	status = "okay";
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun	spidev0: spi@0 {
156*4882a593Smuzhiyun		compatible = "spidev";
157*4882a593Smuzhiyun		reg = <0>;
158*4882a593Smuzhiyun		spi-max-frequency = <5000000>;
159*4882a593Smuzhiyun	};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun	spidev1: spi@1 {
162*4882a593Smuzhiyun		compatible = "spidev";
163*4882a593Smuzhiyun		reg = <1>;
164*4882a593Smuzhiyun		spi-max-frequency = <5000000>;
165*4882a593Smuzhiyun	};
166*4882a593Smuzhiyun};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun&i2c1 {
169*4882a593Smuzhiyun	pinctrl-names = "default";
170*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
171*4882a593Smuzhiyun	clock_frequency = <400000>;
172*4882a593Smuzhiyun	status = "okay";
173*4882a593Smuzhiyun};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun&i2c2 {
176*4882a593Smuzhiyun	pinctrl-names = "default";
177*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
178*4882a593Smuzhiyun	clock_frequency = <400000>;
179*4882a593Smuzhiyun	status = "okay";
180*4882a593Smuzhiyun};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun&lcdif {
183*4882a593Smuzhiyun	pinctrl-names = "default";
184*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_lcdif>;
185*4882a593Smuzhiyun	display = <&display0>;
186*4882a593Smuzhiyun	lcd-supply = <&reg_3v3>;
187*4882a593Smuzhiyun	status = "okay";
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	display0: display0 {
190*4882a593Smuzhiyun		bits-per-pixel = <32>;
191*4882a593Smuzhiyun		bus-width = <18>;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun		display-timings {
194*4882a593Smuzhiyun			timing0: timing0 {
195*4882a593Smuzhiyun				clock-frequency = <33000033>;
196*4882a593Smuzhiyun				hactive = <800>;
197*4882a593Smuzhiyun				vactive = <480>;
198*4882a593Smuzhiyun				hback-porch = <96>;
199*4882a593Smuzhiyun				hfront-porch = <96>;
200*4882a593Smuzhiyun				vback-porch = <20>;
201*4882a593Smuzhiyun				vfront-porch = <21>;
202*4882a593Smuzhiyun				hsync-len = <64>;
203*4882a593Smuzhiyun				vsync-len = <4>;
204*4882a593Smuzhiyun				de-active = <1>;
205*4882a593Smuzhiyun				pixelclk-active = <0>;
206*4882a593Smuzhiyun			};
207*4882a593Smuzhiyun		};
208*4882a593Smuzhiyun	};
209*4882a593Smuzhiyun};
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun&pwm3 {
212*4882a593Smuzhiyun	pinctrl-names = "default";
213*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm3>;
214*4882a593Smuzhiyun	status = "okay";
215*4882a593Smuzhiyun};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun&snvs_pwrkey {
218*4882a593Smuzhiyun	status = "disabled";
219*4882a593Smuzhiyun};
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun&tsc {
222*4882a593Smuzhiyun	pinctrl-names = "default";
223*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_tsc>;
224*4882a593Smuzhiyun	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
225*4882a593Smuzhiyun	measure-delay-time = <0xffff>;
226*4882a593Smuzhiyun	pre-charge-time = <0xffff>;
227*4882a593Smuzhiyun	status = "okay";
228*4882a593Smuzhiyun};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun&uart1 {
231*4882a593Smuzhiyun	pinctrl-names = "default";
232*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
233*4882a593Smuzhiyun	status = "okay";
234*4882a593Smuzhiyun};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun&uart2 {
237*4882a593Smuzhiyun	pinctrl-names = "default";
238*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
239*4882a593Smuzhiyun	status = "okay";
240*4882a593Smuzhiyun};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun&usbotg1 {
243*4882a593Smuzhiyun	pinctrl-names = "default";
244*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg1_id>;
245*4882a593Smuzhiyun	vbus-supply = <&reg_usbotg1_vbus>;
246*4882a593Smuzhiyun	dr_mode = "otg";
247*4882a593Smuzhiyun	disable-over-current;
248*4882a593Smuzhiyun	status = "okay";
249*4882a593Smuzhiyun};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun&usbotg2 {
252*4882a593Smuzhiyun	vbus-supply = <&reg_usbotg2_vbus>;
253*4882a593Smuzhiyun	dr_mode = "host";
254*4882a593Smuzhiyun	disable-over-current;
255*4882a593Smuzhiyun	status = "okay";
256*4882a593Smuzhiyun};
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun&iomuxc {
259*4882a593Smuzhiyun	pinctrl-names = "default";
260*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_gpios>;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun	pinctrl_ecspi4: ecspi4grp {
263*4882a593Smuzhiyun		fsl,pins = <
264*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK	0x1b0b0
265*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI	0x1b0b0
266*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA06__ECSPI4_MISO	0x1b0b0
267*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA01__GPIO4_IO03	0x1b0b0
268*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA07__GPIO4_IO09	0x1b0b0
269*4882a593Smuzhiyun		>;
270*4882a593Smuzhiyun	};
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun	pinctrl_flexcan1: flexcan1grp {
273*4882a593Smuzhiyun		fsl,pins = <
274*4882a593Smuzhiyun			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x0b0b0
275*4882a593Smuzhiyun			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x0b0b0
276*4882a593Smuzhiyun		>;
277*4882a593Smuzhiyun	};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun	pinctrl_flexcan2: flexcan2grp {
280*4882a593Smuzhiyun		fsl,pins = <
281*4882a593Smuzhiyun			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x0b0b0
282*4882a593Smuzhiyun			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x0b0b0
283*4882a593Smuzhiyun		>;
284*4882a593Smuzhiyun	};
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun	pinctrl_gpios: gpiosgrp {
287*4882a593Smuzhiyun		fsl,pins = <
288*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09	0x0b0b0
289*4882a593Smuzhiyun			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x0b0b0
290*4882a593Smuzhiyun			MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24	0x0b0b0
291*4882a593Smuzhiyun			MX6UL_PAD_NAND_RE_B__GPIO4_IO00		0x0b0b0
292*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO08__GPIO1_IO08	0x0b0b0
293*4882a593Smuzhiyun			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x0b0b0
294*4882a593Smuzhiyun			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x0b0b0
295*4882a593Smuzhiyun			MX6UL_PAD_NAND_WE_B__GPIO4_IO01		0x0b0b0
296*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x0b0b0
297*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x0b0b0
298*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x0b0b0
299*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x0b0b0
300*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x0b0b0
301*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x0b0b0
302*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x0b0b0
303*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x0b0b0
304*4882a593Smuzhiyun		>;
305*4882a593Smuzhiyun	};
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun	pinctrl_gpio_keys: gpiokeysgrp {
308*4882a593Smuzhiyun		fsl,pins = <
309*4882a593Smuzhiyun			MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11	0x0b0b0
310*4882a593Smuzhiyun		>;
311*4882a593Smuzhiyun	};
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
314*4882a593Smuzhiyun		fsl,pins = <
315*4882a593Smuzhiyun			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA	0x4001b8b0
316*4882a593Smuzhiyun			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL	0x4001b8b0
317*4882a593Smuzhiyun		>;
318*4882a593Smuzhiyun	};
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
321*4882a593Smuzhiyun		fsl,pins = <
322*4882a593Smuzhiyun			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA	0x4001b8b0
323*4882a593Smuzhiyun			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL	0x4001b8b0
324*4882a593Smuzhiyun		>;
325*4882a593Smuzhiyun	};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun	pinctrl_lcdif: lcdifgrp {
328*4882a593Smuzhiyun		fsl,pins = <
329*4882a593Smuzhiyun			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x100b1
330*4882a593Smuzhiyun			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x100b1
331*4882a593Smuzhiyun			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x100b1
332*4882a593Smuzhiyun			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x100b1
333*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x100b1
334*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x100b1
335*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x100b1
336*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x100b1
337*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x100b1
338*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x100b1
339*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x100b1
340*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x100b1
341*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x100b1
342*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x100b1
343*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x100b1
344*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x100b1
345*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x100b1
346*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x100b1
347*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x100b1
348*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x100b1
349*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x100b1
350*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x100b1
351*4882a593Smuzhiyun		>;
352*4882a593Smuzhiyun	};
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun	pinctrl_led: ledgrp {
355*4882a593Smuzhiyun		fsl,pins = <
356*4882a593Smuzhiyun			MX6UL_PAD_LCD_RESET__GPIO3_IO04		0x0b0b0
357*4882a593Smuzhiyun		>;
358*4882a593Smuzhiyun	};
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun	pinctrl_pwm3: pwm3grp {
361*4882a593Smuzhiyun		fsl,pins = <
362*4882a593Smuzhiyun			MX6UL_PAD_NAND_ALE__PWM3_OUT		0x1b0b0
363*4882a593Smuzhiyun		>;
364*4882a593Smuzhiyun	};
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun	pinctrl_tsc: tscgrp {
367*4882a593Smuzhiyun		fsl,pins = <
368*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01       0xb0
369*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02       0xb0
370*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03       0xb0
371*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04       0xb0
372*4882a593Smuzhiyun		>;
373*4882a593Smuzhiyun	};
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun	pinctrl_uart1: uart1grp {
376*4882a593Smuzhiyun		fsl,pins = <
377*4882a593Smuzhiyun			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
378*4882a593Smuzhiyun			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
379*4882a593Smuzhiyun		>;
380*4882a593Smuzhiyun	};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
383*4882a593Smuzhiyun		fsl,pins = <
384*4882a593Smuzhiyun			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
385*4882a593Smuzhiyun			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
386*4882a593Smuzhiyun		>;
387*4882a593Smuzhiyun	};
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun	pinctrl_usbotg1_id: usbotg1idgrp {
390*4882a593Smuzhiyun		fsl,pins = <
391*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x1b0b0
392*4882a593Smuzhiyun		>;
393*4882a593Smuzhiyun	};
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun	pinctrl_usbotg1_vbus: usbotg1vbusgrp {
396*4882a593Smuzhiyun		fsl,pins = <
397*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO05__GPIO1_IO05	0x1b0b0
398*4882a593Smuzhiyun		>;
399*4882a593Smuzhiyun	};
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun	pinctrl_usbotg2_vbus: usbotg2vbusgrp {
402*4882a593Smuzhiyun		fsl,pins = <
403*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x1b0b0
404*4882a593Smuzhiyun		>;
405*4882a593Smuzhiyun	};
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun	pinctrl_w1: w1grp {
408*4882a593Smuzhiyun		fsl,pins = <
409*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x0b0b0
410*4882a593Smuzhiyun		>;
411*4882a593Smuzhiyun	};
412*4882a593Smuzhiyun};
413