xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/imx6sl-evk.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (C) 2013 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as
6*4882a593Smuzhiyun * published by the Free Software Foundation.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/dts-v1/;
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
12*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
13*4882a593Smuzhiyun#include "imx6sl.dtsi"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun/ {
16*4882a593Smuzhiyun	model = "Freescale i.MX6 SoloLite EVK Board";
17*4882a593Smuzhiyun	compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	memory {
20*4882a593Smuzhiyun		reg = <0x80000000 0x40000000>;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	backlight {
24*4882a593Smuzhiyun		compatible = "pwm-backlight";
25*4882a593Smuzhiyun		pwms = <&pwm1 0 5000000>;
26*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
27*4882a593Smuzhiyun		default-brightness-level = <6>;
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	leds {
31*4882a593Smuzhiyun		compatible = "gpio-leds";
32*4882a593Smuzhiyun		pinctrl-names = "default";
33*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_led>;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		user {
36*4882a593Smuzhiyun			label = "debug";
37*4882a593Smuzhiyun			gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
38*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
39*4882a593Smuzhiyun		};
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	regulators {
43*4882a593Smuzhiyun		compatible = "simple-bus";
44*4882a593Smuzhiyun		#address-cells = <1>;
45*4882a593Smuzhiyun		#size-cells = <0>;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun		reg_usb_otg1_vbus: regulator@0 {
48*4882a593Smuzhiyun			compatible = "regulator-fixed";
49*4882a593Smuzhiyun			reg = <0>;
50*4882a593Smuzhiyun			regulator-name = "usb_otg1_vbus";
51*4882a593Smuzhiyun			regulator-min-microvolt = <5000000>;
52*4882a593Smuzhiyun			regulator-max-microvolt = <5000000>;
53*4882a593Smuzhiyun			gpio = <&gpio4 0 0>;
54*4882a593Smuzhiyun			enable-active-high;
55*4882a593Smuzhiyun			vin-supply = <&swbst_reg>;
56*4882a593Smuzhiyun		};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun		reg_usb_otg2_vbus: regulator@1 {
59*4882a593Smuzhiyun			compatible = "regulator-fixed";
60*4882a593Smuzhiyun			reg = <1>;
61*4882a593Smuzhiyun			regulator-name = "usb_otg2_vbus";
62*4882a593Smuzhiyun			regulator-min-microvolt = <5000000>;
63*4882a593Smuzhiyun			regulator-max-microvolt = <5000000>;
64*4882a593Smuzhiyun			gpio = <&gpio4 2 0>;
65*4882a593Smuzhiyun			enable-active-high;
66*4882a593Smuzhiyun			vin-supply = <&swbst_reg>;
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun		reg_aud3v: regulator@2 {
70*4882a593Smuzhiyun			compatible = "regulator-fixed";
71*4882a593Smuzhiyun			reg = <2>;
72*4882a593Smuzhiyun			regulator-name = "wm8962-supply-3v15";
73*4882a593Smuzhiyun			regulator-min-microvolt = <3150000>;
74*4882a593Smuzhiyun			regulator-max-microvolt = <3150000>;
75*4882a593Smuzhiyun			regulator-boot-on;
76*4882a593Smuzhiyun		};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun		reg_aud4v: regulator@3 {
79*4882a593Smuzhiyun			compatible = "regulator-fixed";
80*4882a593Smuzhiyun			reg = <3>;
81*4882a593Smuzhiyun			regulator-name = "wm8962-supply-4v2";
82*4882a593Smuzhiyun			regulator-min-microvolt = <4325000>;
83*4882a593Smuzhiyun			regulator-max-microvolt = <4325000>;
84*4882a593Smuzhiyun			regulator-boot-on;
85*4882a593Smuzhiyun		};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun		reg_lcd_3v3: regulator@4 {
88*4882a593Smuzhiyun			compatible = "regulator-fixed";
89*4882a593Smuzhiyun			reg = <4>;
90*4882a593Smuzhiyun			regulator-name = "lcd-3v3";
91*4882a593Smuzhiyun			gpio = <&gpio4 3 0>;
92*4882a593Smuzhiyun			enable-active-high;
93*4882a593Smuzhiyun		};
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun	sound {
97*4882a593Smuzhiyun		compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
98*4882a593Smuzhiyun		model = "wm8962-audio";
99*4882a593Smuzhiyun		ssi-controller = <&ssi2>;
100*4882a593Smuzhiyun		audio-codec = <&codec>;
101*4882a593Smuzhiyun		audio-routing =
102*4882a593Smuzhiyun			"Headphone Jack", "HPOUTL",
103*4882a593Smuzhiyun			"Headphone Jack", "HPOUTR",
104*4882a593Smuzhiyun			"Ext Spk", "SPKOUTL",
105*4882a593Smuzhiyun			"Ext Spk", "SPKOUTR",
106*4882a593Smuzhiyun			"AMIC", "MICBIAS",
107*4882a593Smuzhiyun			"IN3R", "AMIC";
108*4882a593Smuzhiyun		mux-int-port = <2>;
109*4882a593Smuzhiyun		mux-ext-port = <3>;
110*4882a593Smuzhiyun	};
111*4882a593Smuzhiyun};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun&audmux {
114*4882a593Smuzhiyun	pinctrl-names = "default";
115*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux3>;
116*4882a593Smuzhiyun	status = "okay";
117*4882a593Smuzhiyun};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun&ecspi1 {
120*4882a593Smuzhiyun	cs-gpios = <&gpio4 11 0>;
121*4882a593Smuzhiyun	pinctrl-names = "default";
122*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
123*4882a593Smuzhiyun	status = "okay";
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun	flash: m25p80@0 {
126*4882a593Smuzhiyun		#address-cells = <1>;
127*4882a593Smuzhiyun		#size-cells = <1>;
128*4882a593Smuzhiyun		compatible = "st,m25p32", "jedec,spi-nor";
129*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
130*4882a593Smuzhiyun		reg = <0>;
131*4882a593Smuzhiyun	};
132*4882a593Smuzhiyun};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun&fec {
135*4882a593Smuzhiyun	pinctrl-names = "default", "sleep";
136*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_fec>;
137*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_fec_sleep>;
138*4882a593Smuzhiyun	phy-mode = "rmii";
139*4882a593Smuzhiyun	status = "okay";
140*4882a593Smuzhiyun};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun&i2c1 {
143*4882a593Smuzhiyun	clock-frequency = <100000>;
144*4882a593Smuzhiyun	pinctrl-names = "default";
145*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
146*4882a593Smuzhiyun	status = "okay";
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun	pmic: pfuze100@08 {
149*4882a593Smuzhiyun		compatible = "fsl,pfuze100";
150*4882a593Smuzhiyun		reg = <0x08>;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun		regulators {
153*4882a593Smuzhiyun			sw1a_reg: sw1ab {
154*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
155*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
156*4882a593Smuzhiyun				regulator-boot-on;
157*4882a593Smuzhiyun				regulator-always-on;
158*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
159*4882a593Smuzhiyun			};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun			sw1c_reg: sw1c {
162*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
163*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
164*4882a593Smuzhiyun				regulator-boot-on;
165*4882a593Smuzhiyun				regulator-always-on;
166*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
167*4882a593Smuzhiyun			};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun			sw2_reg: sw2 {
170*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
171*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
172*4882a593Smuzhiyun				regulator-boot-on;
173*4882a593Smuzhiyun				regulator-always-on;
174*4882a593Smuzhiyun			};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun			sw3a_reg: sw3a {
177*4882a593Smuzhiyun				regulator-min-microvolt = <400000>;
178*4882a593Smuzhiyun				regulator-max-microvolt = <1975000>;
179*4882a593Smuzhiyun				regulator-boot-on;
180*4882a593Smuzhiyun				regulator-always-on;
181*4882a593Smuzhiyun			};
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun			sw3b_reg: sw3b {
184*4882a593Smuzhiyun				regulator-min-microvolt = <400000>;
185*4882a593Smuzhiyun				regulator-max-microvolt = <1975000>;
186*4882a593Smuzhiyun				regulator-boot-on;
187*4882a593Smuzhiyun				regulator-always-on;
188*4882a593Smuzhiyun			};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun			sw4_reg: sw4 {
191*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
192*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
193*4882a593Smuzhiyun			};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun			swbst_reg: swbst {
196*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
197*4882a593Smuzhiyun				regulator-max-microvolt = <5150000>;
198*4882a593Smuzhiyun			};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun			snvs_reg: vsnvs {
201*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
202*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
203*4882a593Smuzhiyun				regulator-boot-on;
204*4882a593Smuzhiyun				regulator-always-on;
205*4882a593Smuzhiyun			};
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun			vref_reg: vrefddr {
208*4882a593Smuzhiyun				regulator-boot-on;
209*4882a593Smuzhiyun				regulator-always-on;
210*4882a593Smuzhiyun			};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun			vgen1_reg: vgen1 {
213*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
214*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
215*4882a593Smuzhiyun				regulator-always-on;
216*4882a593Smuzhiyun			};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun			vgen2_reg: vgen2 {
219*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
220*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
221*4882a593Smuzhiyun			};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun			vgen3_reg: vgen3 {
224*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
225*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
226*4882a593Smuzhiyun			};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun			vgen4_reg: vgen4 {
229*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
230*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
231*4882a593Smuzhiyun				regulator-always-on;
232*4882a593Smuzhiyun			};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun			vgen5_reg: vgen5 {
235*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
236*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
237*4882a593Smuzhiyun				regulator-always-on;
238*4882a593Smuzhiyun			};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun			vgen6_reg: vgen6 {
241*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
242*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
243*4882a593Smuzhiyun				regulator-always-on;
244*4882a593Smuzhiyun			};
245*4882a593Smuzhiyun		};
246*4882a593Smuzhiyun	};
247*4882a593Smuzhiyun};
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun&i2c2 {
250*4882a593Smuzhiyun	clock-frequency = <100000>;
251*4882a593Smuzhiyun	pinctrl-names = "default";
252*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
253*4882a593Smuzhiyun	status = "okay";
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun	codec: wm8962@1a {
256*4882a593Smuzhiyun		compatible = "wlf,wm8962";
257*4882a593Smuzhiyun		reg = <0x1a>;
258*4882a593Smuzhiyun		clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
259*4882a593Smuzhiyun		DCVDD-supply = <&vgen3_reg>;
260*4882a593Smuzhiyun		DBVDD-supply = <&reg_aud3v>;
261*4882a593Smuzhiyun		AVDD-supply = <&vgen3_reg>;
262*4882a593Smuzhiyun		CPVDD-supply = <&vgen3_reg>;
263*4882a593Smuzhiyun		MICVDD-supply = <&reg_aud3v>;
264*4882a593Smuzhiyun		PLLVDD-supply = <&vgen3_reg>;
265*4882a593Smuzhiyun		SPKVDD1-supply = <&reg_aud4v>;
266*4882a593Smuzhiyun		SPKVDD2-supply = <&reg_aud4v>;
267*4882a593Smuzhiyun	};
268*4882a593Smuzhiyun};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun&iomuxc {
271*4882a593Smuzhiyun	pinctrl-names = "default";
272*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hog>;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun	imx6sl-evk {
275*4882a593Smuzhiyun		pinctrl_hog: hoggrp {
276*4882a593Smuzhiyun			fsl,pins = <
277*4882a593Smuzhiyun				MX6SL_PAD_KEY_ROW7__GPIO4_IO07    0x17059
278*4882a593Smuzhiyun				MX6SL_PAD_KEY_COL7__GPIO4_IO06    0x17059
279*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT7__GPIO5_IO00    0x17059
280*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT6__GPIO4_IO29    0x17059
281*4882a593Smuzhiyun				MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
282*4882a593Smuzhiyun				MX6SL_PAD_KEY_COL4__GPIO4_IO00	0x80000000
283*4882a593Smuzhiyun				MX6SL_PAD_KEY_COL5__GPIO4_IO02	0x80000000
284*4882a593Smuzhiyun				MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
285*4882a593Smuzhiyun			>;
286*4882a593Smuzhiyun		};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun		pinctrl_audmux3: audmux3grp {
289*4882a593Smuzhiyun			fsl,pins = <
290*4882a593Smuzhiyun				MX6SL_PAD_AUD_RXD__AUD3_RXD	  0x4130b0
291*4882a593Smuzhiyun				MX6SL_PAD_AUD_TXC__AUD3_TXC	  0x4130b0
292*4882a593Smuzhiyun				MX6SL_PAD_AUD_TXD__AUD3_TXD	  0x4110b0
293*4882a593Smuzhiyun				MX6SL_PAD_AUD_TXFS__AUD3_TXFS	  0x4130b0
294*4882a593Smuzhiyun			>;
295*4882a593Smuzhiyun		};
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun		pinctrl_ecspi1: ecspi1grp {
298*4882a593Smuzhiyun			fsl,pins = <
299*4882a593Smuzhiyun				MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO	0x100b1
300*4882a593Smuzhiyun				MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI	0x100b1
301*4882a593Smuzhiyun				MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK	0x100b1
302*4882a593Smuzhiyun				MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11	0x80000000
303*4882a593Smuzhiyun			>;
304*4882a593Smuzhiyun		};
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun		pinctrl_fec: fecgrp {
307*4882a593Smuzhiyun			fsl,pins = <
308*4882a593Smuzhiyun				MX6SL_PAD_FEC_MDC__FEC_MDC		0x1b0b0
309*4882a593Smuzhiyun				MX6SL_PAD_FEC_MDIO__FEC_MDIO		0x1b0b0
310*4882a593Smuzhiyun				MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV		0x1b0b0
311*4882a593Smuzhiyun				MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0	0x1b0b0
312*4882a593Smuzhiyun				MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1	0x1b0b0
313*4882a593Smuzhiyun				MX6SL_PAD_FEC_TX_EN__FEC_TX_EN		0x1b0b0
314*4882a593Smuzhiyun				MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0	0x1b0b0
315*4882a593Smuzhiyun				MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1	0x1b0b0
316*4882a593Smuzhiyun				MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT	0x4001b0a8
317*4882a593Smuzhiyun			>;
318*4882a593Smuzhiyun		};
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun		pinctrl_fec_sleep: fecgrp-sleep {
321*4882a593Smuzhiyun			fsl,pins = <
322*4882a593Smuzhiyun				MX6SL_PAD_FEC_MDC__GPIO4_IO23      0x3080
323*4882a593Smuzhiyun				MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25   0x3080
324*4882a593Smuzhiyun				MX6SL_PAD_FEC_RXD0__GPIO4_IO17     0x3080
325*4882a593Smuzhiyun				MX6SL_PAD_FEC_RXD1__GPIO4_IO18     0x3080
326*4882a593Smuzhiyun				MX6SL_PAD_FEC_TX_EN__GPIO4_IO22    0x3080
327*4882a593Smuzhiyun				MX6SL_PAD_FEC_TXD0__GPIO4_IO24     0x3080
328*4882a593Smuzhiyun				MX6SL_PAD_FEC_TXD1__GPIO4_IO16     0x3080
329*4882a593Smuzhiyun				MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26  0x3080
330*4882a593Smuzhiyun			>;
331*4882a593Smuzhiyun		};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun		pinctrl_i2c1: i2c1grp {
334*4882a593Smuzhiyun			fsl,pins = <
335*4882a593Smuzhiyun				MX6SL_PAD_I2C1_SCL__I2C1_SCL	0x4001b8b1
336*4882a593Smuzhiyun				MX6SL_PAD_I2C1_SDA__I2C1_SDA	0x4001b8b1
337*4882a593Smuzhiyun			>;
338*4882a593Smuzhiyun		};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun		pinctrl_i2c2: i2c2grp {
342*4882a593Smuzhiyun			fsl,pins = <
343*4882a593Smuzhiyun				MX6SL_PAD_I2C2_SCL__I2C2_SCL	0x4001b8b1
344*4882a593Smuzhiyun				MX6SL_PAD_I2C2_SDA__I2C2_SDA	0x4001b8b1
345*4882a593Smuzhiyun			>;
346*4882a593Smuzhiyun		};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun		pinctrl_kpp: kppgrp {
349*4882a593Smuzhiyun			fsl,pins = <
350*4882a593Smuzhiyun				MX6SL_PAD_KEY_ROW0__KEY_ROW0    0x1b010
351*4882a593Smuzhiyun				MX6SL_PAD_KEY_ROW1__KEY_ROW1    0x1b010
352*4882a593Smuzhiyun				MX6SL_PAD_KEY_ROW2__KEY_ROW2    0x1b0b0
353*4882a593Smuzhiyun				MX6SL_PAD_KEY_COL0__KEY_COL0    0x110b0
354*4882a593Smuzhiyun				MX6SL_PAD_KEY_COL1__KEY_COL1    0x110b0
355*4882a593Smuzhiyun				MX6SL_PAD_KEY_COL2__KEY_COL2    0x110b0
356*4882a593Smuzhiyun			>;
357*4882a593Smuzhiyun		};
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun		pinctrl_lcd: lcdgrp {
360*4882a593Smuzhiyun			fsl,pins = <
361*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
362*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
363*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
364*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
365*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
366*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
367*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
368*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
369*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
370*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
371*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
372*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
373*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
374*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
375*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
376*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
377*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
378*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
379*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
380*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
381*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
382*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
383*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
384*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
385*4882a593Smuzhiyun				MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
386*4882a593Smuzhiyun				MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
387*4882a593Smuzhiyun				MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
388*4882a593Smuzhiyun				MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
389*4882a593Smuzhiyun			>;
390*4882a593Smuzhiyun		};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun		pinctrl_led: ledgrp {
393*4882a593Smuzhiyun			fsl,pins = <
394*4882a593Smuzhiyun				MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
395*4882a593Smuzhiyun			>;
396*4882a593Smuzhiyun		};
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun		pinctrl_pwm1: pwmgrp {
399*4882a593Smuzhiyun			fsl,pins = <
400*4882a593Smuzhiyun				MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
401*4882a593Smuzhiyun			>;
402*4882a593Smuzhiyun		};
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun		pinctrl_uart1: uart1grp {
405*4882a593Smuzhiyun			fsl,pins = <
406*4882a593Smuzhiyun				MX6SL_PAD_UART1_RXD__UART1_RX_DATA	0x1b0b1
407*4882a593Smuzhiyun				MX6SL_PAD_UART1_TXD__UART1_TX_DATA	0x1b0b1
408*4882a593Smuzhiyun			>;
409*4882a593Smuzhiyun		};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun		pinctrl_usbotg1: usbotg1grp {
412*4882a593Smuzhiyun			fsl,pins = <
413*4882a593Smuzhiyun				MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID	0x17059
414*4882a593Smuzhiyun			>;
415*4882a593Smuzhiyun		};
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun		pinctrl_usdhc1: usdhc1grp {
418*4882a593Smuzhiyun			fsl,pins = <
419*4882a593Smuzhiyun				MX6SL_PAD_SD1_CMD__SD1_CMD		0x17059
420*4882a593Smuzhiyun				MX6SL_PAD_SD1_CLK__SD1_CLK		0x10059
421*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT0__SD1_DATA0		0x17059
422*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT1__SD1_DATA1		0x17059
423*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT2__SD1_DATA2		0x17059
424*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT3__SD1_DATA3		0x17059
425*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT4__SD1_DATA4		0x17059
426*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT5__SD1_DATA5		0x17059
427*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT6__SD1_DATA6		0x17059
428*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT7__SD1_DATA7		0x17059
429*4882a593Smuzhiyun			>;
430*4882a593Smuzhiyun		};
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
433*4882a593Smuzhiyun			fsl,pins = <
434*4882a593Smuzhiyun				MX6SL_PAD_SD1_CMD__SD1_CMD		0x170b9
435*4882a593Smuzhiyun				MX6SL_PAD_SD1_CLK__SD1_CLK		0x100b9
436*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT0__SD1_DATA0		0x170b9
437*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT1__SD1_DATA1		0x170b9
438*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT2__SD1_DATA2		0x170b9
439*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT3__SD1_DATA3		0x170b9
440*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT4__SD1_DATA4		0x170b9
441*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT5__SD1_DATA5		0x170b9
442*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT6__SD1_DATA6		0x170b9
443*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT7__SD1_DATA7		0x170b9
444*4882a593Smuzhiyun			>;
445*4882a593Smuzhiyun		};
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
448*4882a593Smuzhiyun			fsl,pins = <
449*4882a593Smuzhiyun				MX6SL_PAD_SD1_CMD__SD1_CMD		0x170f9
450*4882a593Smuzhiyun				MX6SL_PAD_SD1_CLK__SD1_CLK		0x100f9
451*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT0__SD1_DATA0		0x170f9
452*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT1__SD1_DATA1		0x170f9
453*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT2__SD1_DATA2		0x170f9
454*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT3__SD1_DATA3		0x170f9
455*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT4__SD1_DATA4		0x170f9
456*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT5__SD1_DATA5		0x170f9
457*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT6__SD1_DATA6		0x170f9
458*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT7__SD1_DATA7		0x170f9
459*4882a593Smuzhiyun			>;
460*4882a593Smuzhiyun		};
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun		pinctrl_usdhc2: usdhc2grp {
463*4882a593Smuzhiyun			fsl,pins = <
464*4882a593Smuzhiyun				MX6SL_PAD_SD2_CMD__SD2_CMD		0x17059
465*4882a593Smuzhiyun				MX6SL_PAD_SD2_CLK__SD2_CLK		0x10059
466*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x17059
467*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x17059
468*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x17059
469*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x17059
470*4882a593Smuzhiyun			>;
471*4882a593Smuzhiyun		};
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
474*4882a593Smuzhiyun			fsl,pins = <
475*4882a593Smuzhiyun				MX6SL_PAD_SD2_CMD__SD2_CMD		0x170b9
476*4882a593Smuzhiyun				MX6SL_PAD_SD2_CLK__SD2_CLK		0x100b9
477*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x170b9
478*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x170b9
479*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x170b9
480*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x170b9
481*4882a593Smuzhiyun			>;
482*4882a593Smuzhiyun		};
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
485*4882a593Smuzhiyun			fsl,pins = <
486*4882a593Smuzhiyun				MX6SL_PAD_SD2_CMD__SD2_CMD		0x170f9
487*4882a593Smuzhiyun				MX6SL_PAD_SD2_CLK__SD2_CLK		0x100f9
488*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x170f9
489*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x170f9
490*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x170f9
491*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x170f9
492*4882a593Smuzhiyun			>;
493*4882a593Smuzhiyun		};
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun		pinctrl_usdhc3: usdhc3grp {
496*4882a593Smuzhiyun			fsl,pins = <
497*4882a593Smuzhiyun				MX6SL_PAD_SD3_CMD__SD3_CMD		0x17059
498*4882a593Smuzhiyun				MX6SL_PAD_SD3_CLK__SD3_CLK		0x10059
499*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x17059
500*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x17059
501*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x17059
502*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x17059
503*4882a593Smuzhiyun			>;
504*4882a593Smuzhiyun		};
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
507*4882a593Smuzhiyun			fsl,pins = <
508*4882a593Smuzhiyun				MX6SL_PAD_SD3_CMD__SD3_CMD		0x170b9
509*4882a593Smuzhiyun				MX6SL_PAD_SD3_CLK__SD3_CLK		0x100b9
510*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
511*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
512*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
513*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
514*4882a593Smuzhiyun			>;
515*4882a593Smuzhiyun		};
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
518*4882a593Smuzhiyun			fsl,pins = <
519*4882a593Smuzhiyun				MX6SL_PAD_SD3_CMD__SD3_CMD		0x170f9
520*4882a593Smuzhiyun				MX6SL_PAD_SD3_CLK__SD3_CLK		0x100f9
521*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
522*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
523*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
524*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
525*4882a593Smuzhiyun			>;
526*4882a593Smuzhiyun		};
527*4882a593Smuzhiyun	};
528*4882a593Smuzhiyun};
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun&kpp {
531*4882a593Smuzhiyun	pinctrl-names = "default";
532*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_kpp>;
533*4882a593Smuzhiyun	linux,keymap = <
534*4882a593Smuzhiyun			MATRIX_KEY(0x0, 0x0, KEY_UP)         /* ROW0, COL0 */
535*4882a593Smuzhiyun			MATRIX_KEY(0x0, 0x1, KEY_DOWN)       /* ROW0, COL1 */
536*4882a593Smuzhiyun			MATRIX_KEY(0x0, 0x2, KEY_ENTER)      /* ROW0, COL2 */
537*4882a593Smuzhiyun			MATRIX_KEY(0x1, 0x0, KEY_HOME)       /* ROW1, COL0 */
538*4882a593Smuzhiyun			MATRIX_KEY(0x1, 0x1, KEY_RIGHT)      /* ROW1, COL1 */
539*4882a593Smuzhiyun			MATRIX_KEY(0x1, 0x2, KEY_LEFT)       /* ROW1, COL2 */
540*4882a593Smuzhiyun			MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
541*4882a593Smuzhiyun			MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP)   /* ROW2, COL1 */
542*4882a593Smuzhiyun	>;
543*4882a593Smuzhiyun	status = "okay";
544*4882a593Smuzhiyun};
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun&lcdif {
547*4882a593Smuzhiyun	pinctrl-names = "default";
548*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_lcd>;
549*4882a593Smuzhiyun	lcd-supply = <&reg_lcd_3v3>;
550*4882a593Smuzhiyun	display = <&display0>;
551*4882a593Smuzhiyun	status = "okay";
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun	display0: display0 {
554*4882a593Smuzhiyun		bits-per-pixel = <32>;
555*4882a593Smuzhiyun		bus-width = <24>;
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun		display-timings {
558*4882a593Smuzhiyun			native-mode = <&timing0>;
559*4882a593Smuzhiyun			timing0: timing0 {
560*4882a593Smuzhiyun				clock-frequency = <33500000>;
561*4882a593Smuzhiyun				hactive = <800>;
562*4882a593Smuzhiyun				vactive = <480>;
563*4882a593Smuzhiyun				hback-porch = <89>;
564*4882a593Smuzhiyun				hfront-porch = <164>;
565*4882a593Smuzhiyun				vback-porch = <23>;
566*4882a593Smuzhiyun				vfront-porch = <10>;
567*4882a593Smuzhiyun				hsync-len = <10>;
568*4882a593Smuzhiyun				vsync-len = <10>;
569*4882a593Smuzhiyun				hsync-active = <0>;
570*4882a593Smuzhiyun				vsync-active = <0>;
571*4882a593Smuzhiyun				de-active = <1>;
572*4882a593Smuzhiyun				pixelclk-active = <0>;
573*4882a593Smuzhiyun			};
574*4882a593Smuzhiyun		};
575*4882a593Smuzhiyun	};
576*4882a593Smuzhiyun};
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun&pwm1 {
579*4882a593Smuzhiyun	pinctrl-names = "default";
580*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
581*4882a593Smuzhiyun	status = "okay";
582*4882a593Smuzhiyun};
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun&snvs_poweroff {
585*4882a593Smuzhiyun	status = "okay";
586*4882a593Smuzhiyun};
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun&ssi2 {
589*4882a593Smuzhiyun	status = "okay";
590*4882a593Smuzhiyun};
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun&uart1 {
593*4882a593Smuzhiyun	pinctrl-names = "default";
594*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
595*4882a593Smuzhiyun	status = "okay";
596*4882a593Smuzhiyun};
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun&usbotg1 {
599*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg1_vbus>;
600*4882a593Smuzhiyun	pinctrl-names = "default";
601*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg1>;
602*4882a593Smuzhiyun	disable-over-current;
603*4882a593Smuzhiyun	status = "okay";
604*4882a593Smuzhiyun};
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun&usbotg2 {
607*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg2_vbus>;
608*4882a593Smuzhiyun	dr_mode = "host";
609*4882a593Smuzhiyun	disable-over-current;
610*4882a593Smuzhiyun	status = "okay";
611*4882a593Smuzhiyun};
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun&usdhc1 {
614*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
615*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
616*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
617*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
618*4882a593Smuzhiyun	bus-width = <8>;
619*4882a593Smuzhiyun	cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
620*4882a593Smuzhiyun	wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
621*4882a593Smuzhiyun	status = "okay";
622*4882a593Smuzhiyun};
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun&usdhc2 {
625*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
626*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
627*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
628*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
629*4882a593Smuzhiyun	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
630*4882a593Smuzhiyun	wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
631*4882a593Smuzhiyun	status = "okay";
632*4882a593Smuzhiyun};
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun&usdhc3 {
635*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
636*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
637*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
638*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
639*4882a593Smuzhiyun	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
640*4882a593Smuzhiyun	status = "okay";
641*4882a593Smuzhiyun};
642