1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright 2013 CompuLab Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Author: Valentin Raevsky <valentin@compulab.co.il> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * The code contained herein is licensed under the GNU General Public 7*4882a593Smuzhiyun * License. You may obtain a copy of the GNU General Public License 8*4882a593Smuzhiyun * Version 2 or later at the following locations: 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * http://www.opensource.org/licenses/gpl-license.html 11*4882a593Smuzhiyun * http://www.gnu.org/copyleft/gpl.html 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/dts-v1/; 15*4882a593Smuzhiyun#include "imx6q.dtsi" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun/ { 18*4882a593Smuzhiyun model = "CompuLab CM-FX6"; 19*4882a593Smuzhiyun compatible = "compulab,cm-fx6", "fsl,imx6q"; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun memory { 22*4882a593Smuzhiyun reg = <0x10000000 0x80000000>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun leds { 26*4882a593Smuzhiyun compatible = "gpio-leds"; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun heartbeat-led { 29*4882a593Smuzhiyun label = "Heartbeat"; 30*4882a593Smuzhiyun gpios = <&gpio2 31 0>; 31*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun}; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun&fec { 37*4882a593Smuzhiyun pinctrl-names = "default"; 38*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 39*4882a593Smuzhiyun phy-mode = "rgmii"; 40*4882a593Smuzhiyun status = "okay"; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun&gpmi { 44*4882a593Smuzhiyun pinctrl-names = "default"; 45*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpmi_nand>; 46*4882a593Smuzhiyun status = "okay"; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun&iomuxc { 50*4882a593Smuzhiyun imx6q-cm-fx6 { 51*4882a593Smuzhiyun pinctrl_enet: enetgrp { 52*4882a593Smuzhiyun fsl,pins = < 53*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 54*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 55*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 56*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 57*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 58*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 59*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 60*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 61*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 62*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 63*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 64*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 65*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 66*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 67*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 68*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 69*4882a593Smuzhiyun >; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun pinctrl_gpmi_nand: gpminandgrp { 73*4882a593Smuzhiyun fsl,pins = < 74*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 75*4882a593Smuzhiyun MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 76*4882a593Smuzhiyun MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 77*4882a593Smuzhiyun MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 78*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 79*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 80*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 81*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 82*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 83*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 84*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 85*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 86*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 87*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 88*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 89*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 90*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 91*4882a593Smuzhiyun >; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun pinctrl_uart4: uart4grp { 95*4882a593Smuzhiyun fsl,pins = < 96*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 97*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 98*4882a593Smuzhiyun >; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun}; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun&uart4 { 104*4882a593Smuzhiyun pinctrl-names = "default"; 105*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart4>; 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun}; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun&sata { 110*4882a593Smuzhiyun status = "okay"; 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun&usdhc3 { 114*4882a593Smuzhiyun status = "okay"; 115*4882a593Smuzhiyun}; 116