1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright 2016 Beckhoff Automation 3*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * Copyright 2011 Linaro Ltd. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * The code contained herein is licensed under the GNU General Public 7*4882a593Smuzhiyun * License. You may obtain a copy of the GNU General Public License 8*4882a593Smuzhiyun * Version 2 or later at the following locations: 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * http://www.opensource.org/licenses/gpl-license.html 11*4882a593Smuzhiyun * http://www.gnu.org/copyleft/gpl.html 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun#include "skeleton.dtsi" 15*4882a593Smuzhiyun#include "imx53-pinfunc.h" 16*4882a593Smuzhiyun#include <dt-bindings/clock/imx5-clock.h> 17*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 18*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 19*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun/ { 22*4882a593Smuzhiyun aliases { 23*4882a593Smuzhiyun serial1 = &uart2; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun soc { 27*4882a593Smuzhiyun #address-cells = <1>; 28*4882a593Smuzhiyun #size-cells = <1>; 29*4882a593Smuzhiyun compatible = "simple-bus"; 30*4882a593Smuzhiyun ranges; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun aips@50000000 { /* AIPS1 */ 33*4882a593Smuzhiyun compatible = "fsl,aips-bus", "simple-bus"; 34*4882a593Smuzhiyun #address-cells = <1>; 35*4882a593Smuzhiyun #size-cells = <1>; 36*4882a593Smuzhiyun reg = <0x50000000 0x10000000>; 37*4882a593Smuzhiyun ranges; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun iomuxc: iomuxc@53fa8000 { 40*4882a593Smuzhiyun compatible = "fsl,imx53-iomuxc"; 41*4882a593Smuzhiyun reg = <0x53fa8000 0x4000>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun gpr: iomuxc-gpr@53fa8000 { 45*4882a593Smuzhiyun compatible = "fsl,imx53-iomuxc-gpr", "syscon"; 46*4882a593Smuzhiyun reg = <0x53fa8000 0xc>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun uart2: serial@53fc0000 { 50*4882a593Smuzhiyun compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart"; 51*4882a593Smuzhiyun reg = <0x53fc0000 0x4000>; 52*4882a593Smuzhiyun interrupts = <32>; 53*4882a593Smuzhiyun clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, 54*4882a593Smuzhiyun <&clks IMX5_CLK_UART2_PER_GATE>; 55*4882a593Smuzhiyun clock-names = "ipg", "per"; 56*4882a593Smuzhiyun dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; 57*4882a593Smuzhiyun dma-names = "rx", "tx"; 58*4882a593Smuzhiyun status = "disabled"; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun clks: ccm@53fd4000{ 62*4882a593Smuzhiyun compatible = "fsl,imx53-ccm"; 63*4882a593Smuzhiyun reg = <0x53fd4000 0x4000>; 64*4882a593Smuzhiyun interrupts = <0 71 0x04 0 72 0x04>; 65*4882a593Smuzhiyun #clock-cells = <1>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun gpio7: gpio@53fe4000 { 69*4882a593Smuzhiyun compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 70*4882a593Smuzhiyun reg = <0x53fe4000 0x4000>; 71*4882a593Smuzhiyun interrupts = <107 108>; 72*4882a593Smuzhiyun gpio-controller; 73*4882a593Smuzhiyun #gpio-cells = <2>; 74*4882a593Smuzhiyun interrupt-controller; 75*4882a593Smuzhiyun #interrupt-cells = <2>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun aips@60000000 { /* AIPS2 */ 80*4882a593Smuzhiyun compatible = "fsl,aips-bus", "simple-bus"; 81*4882a593Smuzhiyun #address-cells = <1>; 82*4882a593Smuzhiyun #size-cells = <1>; 83*4882a593Smuzhiyun reg = <0x60000000 0x10000000>; 84*4882a593Smuzhiyun ranges; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun sdma: sdma@63fb0000 { 87*4882a593Smuzhiyun compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; 88*4882a593Smuzhiyun reg = <0x63fb0000 0x4000>; 89*4882a593Smuzhiyun interrupts = <6>; 90*4882a593Smuzhiyun clocks = <&clks IMX5_CLK_SDMA_GATE>, 91*4882a593Smuzhiyun <&clks IMX5_CLK_SDMA_GATE>; 92*4882a593Smuzhiyun clock-names = "ipg", "ahb"; 93*4882a593Smuzhiyun #dma-cells = <3>; 94*4882a593Smuzhiyun fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun fec: ethernet@63fec000 { 99*4882a593Smuzhiyun compatible = "fsl,imx53-fec", "fsl,imx25-fec"; 100*4882a593Smuzhiyun reg = <0x63fec000 0x4000>; 101*4882a593Smuzhiyun interrupts = <87>; 102*4882a593Smuzhiyun clocks = <&clks IMX5_CLK_FEC_GATE>, 103*4882a593Smuzhiyun <&clks IMX5_CLK_FEC_GATE>, 104*4882a593Smuzhiyun <&clks IMX5_CLK_FEC_GATE>; 105*4882a593Smuzhiyun clock-names = "ipg", "ahb", "ptp"; 106*4882a593Smuzhiyun status = "disabled"; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun}; 111