1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Samsung Exynos7420 SoC device tree source 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2016 Samsung Electronics Co., Ltd. 5*4882a593Smuzhiyun * http://www.samsung.com 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/dts-v1/; 11*4882a593Smuzhiyun#include "skeleton.dtsi" 12*4882a593Smuzhiyun#include <dt-bindings/clock/exynos7420-clk.h> 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun compatible = "samsung,exynos7420"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun fin_pll: xxti { 17*4882a593Smuzhiyun compatible = "fixed-clock"; 18*4882a593Smuzhiyun clock-output-names = "fin_pll"; 19*4882a593Smuzhiyun u-boot,dm-pre-reloc; 20*4882a593Smuzhiyun #clock-cells = <0>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun clock_topc: clock-controller@10570000 { 24*4882a593Smuzhiyun compatible = "samsung,exynos7-clock-topc"; 25*4882a593Smuzhiyun reg = <0x10570000 0x10000>; 26*4882a593Smuzhiyun u-boot,dm-pre-reloc; 27*4882a593Smuzhiyun #clock-cells = <1>; 28*4882a593Smuzhiyun clocks = <&fin_pll>; 29*4882a593Smuzhiyun clock-names = "fin_pll"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clock_top0: clock-controller@105d0000 { 33*4882a593Smuzhiyun compatible = "samsung,exynos7-clock-top0"; 34*4882a593Smuzhiyun reg = <0x105d0000 0xb000>; 35*4882a593Smuzhiyun u-boot,dm-pre-reloc; 36*4882a593Smuzhiyun #clock-cells = <1>; 37*4882a593Smuzhiyun clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 38*4882a593Smuzhiyun <&clock_topc DOUT_SCLK_BUS1_PLL>, 39*4882a593Smuzhiyun <&clock_topc DOUT_SCLK_CC_PLL>, 40*4882a593Smuzhiyun <&clock_topc DOUT_SCLK_MFC_PLL>; 41*4882a593Smuzhiyun clock-names = "fin_pll", "dout_sclk_bus0_pll", 42*4882a593Smuzhiyun "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 43*4882a593Smuzhiyun "dout_sclk_mfc_pll"; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun clock_peric1: clock-controller@14c80000 { 47*4882a593Smuzhiyun compatible = "samsung,exynos7-clock-peric1"; 48*4882a593Smuzhiyun reg = <0x14c80000 0xd00>; 49*4882a593Smuzhiyun u-boot,dm-pre-reloc; 50*4882a593Smuzhiyun #clock-cells = <1>; 51*4882a593Smuzhiyun clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, 52*4882a593Smuzhiyun <&clock_top0 CLK_SCLK_UART1>, 53*4882a593Smuzhiyun <&clock_top0 CLK_SCLK_UART2>, 54*4882a593Smuzhiyun <&clock_top0 CLK_SCLK_UART3>; 55*4882a593Smuzhiyun clock-names = "fin_pll", "dout_aclk_peric1_66", 56*4882a593Smuzhiyun "sclk_uart1", "sclk_uart2", "sclk_uart3"; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun pinctrl@13470000 { 60*4882a593Smuzhiyun compatible = "samsung,exynos7420-pinctrl"; 61*4882a593Smuzhiyun reg = <0x13470000 0x1000>; 62*4882a593Smuzhiyun u-boot,dm-pre-reloc; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun serial2_bus: serial2-bus { 65*4882a593Smuzhiyun samsung,pins = "gpd1-4", "gpd1-5"; 66*4882a593Smuzhiyun samsung,pin-function = <2>; 67*4882a593Smuzhiyun samsung,pin-pud = <3>; 68*4882a593Smuzhiyun samsung,pin-drv = <0>; 69*4882a593Smuzhiyun u-boot,dm-pre-reloc; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun serial@14C30000 { 74*4882a593Smuzhiyun compatible = "samsung,exynos4210-uart"; 75*4882a593Smuzhiyun reg = <0x14C30000 0x100>; 76*4882a593Smuzhiyun u-boot,dm-pre-reloc; 77*4882a593Smuzhiyun clocks = <&clock_peric1 PCLK_UART2>, 78*4882a593Smuzhiyun <&clock_peric1 SCLK_UART2>; 79*4882a593Smuzhiyun clock-names = "uart", "clk_uart_baud0"; 80*4882a593Smuzhiyun pinctrl-names = "default"; 81*4882a593Smuzhiyun pinctrl-0 = <&serial2_bus>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun}; 84