xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/exynos5250-spring.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Google Spring board device tree source
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (c) 2013 Google, Inc
5*4882a593Smuzhiyun * Copyright (c) 2014 SUSE LINUX Products GmbH
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier:	GPL-2.0
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/dts-v1/;
11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
12*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
13*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
14*4882a593Smuzhiyun#include "exynos5250.dtsi"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun/ {
17*4882a593Smuzhiyun	model = "Google Spring";
18*4882a593Smuzhiyun	compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5";
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	aliases {
21*4882a593Smuzhiyun		i2c0 = "/i2c@12C60000";
22*4882a593Smuzhiyun		i2c1 = "/i2c@12C70000";
23*4882a593Smuzhiyun		i2c2 = "/i2c@12C80000";
24*4882a593Smuzhiyun		i2c3 = "/i2c@12C90000";
25*4882a593Smuzhiyun		i2c4 = "/i2c@12CA0000";
26*4882a593Smuzhiyun		i2c5 = "/i2c@12CB0000";
27*4882a593Smuzhiyun		i2c6 = "/i2c@12CC0000";
28*4882a593Smuzhiyun		i2c7 = "/i2c@12CD0000";
29*4882a593Smuzhiyun		i2c104 = &cros_ec_ldo_tunnel;
30*4882a593Smuzhiyun		spi0 = "/spi@12d20000";
31*4882a593Smuzhiyun		spi1 = "/spi@12d30000";
32*4882a593Smuzhiyun		spi2 = "/spi@12d40000";
33*4882a593Smuzhiyun		spi3 = "/spi@131a0000";
34*4882a593Smuzhiyun		spi4 = "/spi@131b0000";
35*4882a593Smuzhiyun		mmc0 = "/mmc@12000000";
36*4882a593Smuzhiyun		serial0 = "/serial@12C30000";
37*4882a593Smuzhiyun		console = "/serial@12C30000";
38*4882a593Smuzhiyun		i2s = "/sound@3830000";
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	memory {
42*4882a593Smuzhiyun		reg = <0x40000000 0x80000000>;
43*4882a593Smuzhiyun	};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	flash@0 {
46*4882a593Smuzhiyun		spl { /* spl size override */
47*4882a593Smuzhiyun			size = <0x8000>;
48*4882a593Smuzhiyun		};
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	chosen {
52*4882a593Smuzhiyun		bootargs = "console=tty1";
53*4882a593Smuzhiyun		stdout-path = "serial3:115200n8";
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	board-rev {
57*4882a593Smuzhiyun		compatible = "google,board-revision";
58*4882a593Smuzhiyun		google,board-rev-gpios = <&gpy4 0 0>, <&gpy4 1 0>,
59*4882a593Smuzhiyun					 <&gpy4 2 0>;
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	i2c@12C90000 {
63*4882a593Smuzhiyun		clock-frequency = <100000>;
64*4882a593Smuzhiyun		tpm@20 {
65*4882a593Smuzhiyun			reg = <0x20>;
66*4882a593Smuzhiyun			compatible = "infineon,slb9645tt";
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	mmc@12200000 {
71*4882a593Smuzhiyun		samsung,bus-width = <8>;
72*4882a593Smuzhiyun		samsung,timing = <1 3 3>;
73*4882a593Smuzhiyun		samsung,removable = <0>;
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun	mmc@12210000 {
77*4882a593Smuzhiyun		status = "disabled";
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	mmc@12220000 {
81*4882a593Smuzhiyun		/* MMC2 pins are used as GPIO for eDP bridge */
82*4882a593Smuzhiyun		status = "disabled";
83*4882a593Smuzhiyun	};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun	mmc@12230000 {
86*4882a593Smuzhiyun		status = "disabled";
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun	ehci@12110000 {
90*4882a593Smuzhiyun		samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
91*4882a593Smuzhiyun		status = "okay";
92*4882a593Smuzhiyun	};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun	xhci@12000000 {
95*4882a593Smuzhiyun		samsung,vbus-gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>;
96*4882a593Smuzhiyun	};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun	spi@12d30000 {
99*4882a593Smuzhiyun		spi-max-frequency = <50000000>;
100*4882a593Smuzhiyun		firmware_storage_spi: flash@0 {
101*4882a593Smuzhiyun			compatible = "spi-flash";
102*4882a593Smuzhiyun			reg = <0>;
103*4882a593Smuzhiyun		};
104*4882a593Smuzhiyun	};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun	tmu@10060000 {
107*4882a593Smuzhiyun		samsung,min-temp	= <25>;
108*4882a593Smuzhiyun		samsung,max-temp	= <125>;
109*4882a593Smuzhiyun		samsung,start-warning	= <95>;
110*4882a593Smuzhiyun		samsung,start-tripping	= <105>;
111*4882a593Smuzhiyun		samsung,hw-tripping	= <110>;
112*4882a593Smuzhiyun		samsung,efuse-min-value	= <40>;
113*4882a593Smuzhiyun		samsung,efuse-value	= <55>;
114*4882a593Smuzhiyun		samsung,efuse-max-value	= <100>;
115*4882a593Smuzhiyun		samsung,slope		= <274761730>;
116*4882a593Smuzhiyun		samsung,dc-value	= <25>;
117*4882a593Smuzhiyun	};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun	fimd@14400000 {
120*4882a593Smuzhiyun		samsung,vl-freq = <60>;
121*4882a593Smuzhiyun		samsung,vl-col = <1366>;
122*4882a593Smuzhiyun		samsung,vl-row = <768>;
123*4882a593Smuzhiyun		samsung,vl-width = <1366>;
124*4882a593Smuzhiyun		samsung,vl-height = <768>;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun		samsung,vl-clkp;
127*4882a593Smuzhiyun		samsung,vl-dp;
128*4882a593Smuzhiyun		samsung,vl-hsp;
129*4882a593Smuzhiyun		samsung,vl-vsp;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun		samsung,vl-bpix = <4>;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun		samsung,vl-hspw = <32>;
134*4882a593Smuzhiyun		samsung,vl-hbpd = <80>;
135*4882a593Smuzhiyun		samsung,vl-hfpd = <48>;
136*4882a593Smuzhiyun		samsung,vl-vspw = <5>;
137*4882a593Smuzhiyun		samsung,vl-vbpd = <14>;
138*4882a593Smuzhiyun		samsung,vl-vfpd = <3>;
139*4882a593Smuzhiyun		samsung,vl-cmd-allow-len = <0xf>;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		samsung,winid = <0>;
142*4882a593Smuzhiyun		samsung,interface-mode = <1>;
143*4882a593Smuzhiyun		samsung,dp-enabled = <1>;
144*4882a593Smuzhiyun		samsung,dual-lcd-enabled = <0>;
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun	dp@145b0000 {
148*4882a593Smuzhiyun		samsung,lt-status = <0>;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun		samsung,master-mode = <0>;
151*4882a593Smuzhiyun		samsung,bist-mode = <0>;
152*4882a593Smuzhiyun		samsung,bist-pattern = <0>;
153*4882a593Smuzhiyun		samsung,h-sync-polarity = <0>;
154*4882a593Smuzhiyun		samsung,v-sync-polarity = <0>;
155*4882a593Smuzhiyun		samsung,interlaced = <0>;
156*4882a593Smuzhiyun		samsung,color-space = <0>;
157*4882a593Smuzhiyun		samsung,dynamic-range = <0>;
158*4882a593Smuzhiyun		samsung,ycbcr-coeff = <0>;
159*4882a593Smuzhiyun		samsung,color-depth = <1>;
160*4882a593Smuzhiyun	};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun	backlight: backlight {
163*4882a593Smuzhiyun		compatible = "pwm-backlight";
164*4882a593Smuzhiyun		pwms = <&pwm 0 1000000 0>;
165*4882a593Smuzhiyun		brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
166*4882a593Smuzhiyun		default-brightness-level = <1>;
167*4882a593Smuzhiyun		enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
168*4882a593Smuzhiyun		power-supply = <&fet1>;
169*4882a593Smuzhiyun	};
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun	panel: panel {
172*4882a593Smuzhiyun		compatible = "auo,b116xw03";
173*4882a593Smuzhiyun		power-supply = <&fet6>;
174*4882a593Smuzhiyun		backlight = <&backlight>;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun		port {
177*4882a593Smuzhiyun			panel_in: endpoint {
178*4882a593Smuzhiyun				remote-endpoint = <&bridge_out>;
179*4882a593Smuzhiyun			};
180*4882a593Smuzhiyun		};
181*4882a593Smuzhiyun	};
182*4882a593Smuzhiyun};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun&i2c_0 {
185*4882a593Smuzhiyun	status = "okay";
186*4882a593Smuzhiyun	samsung,i2c-sda-delay = <100>;
187*4882a593Smuzhiyun	samsung,i2c-max-bus-freq = <378000>;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	s5m8767-pmic@66 {
190*4882a593Smuzhiyun		compatible = "samsung,s5m8767-pmic";
191*4882a593Smuzhiyun		reg = <0x66>;
192*4882a593Smuzhiyun		interrupt-parent = <&gpx3>;
193*4882a593Smuzhiyun		wakeup-source;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun		s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */
196*4882a593Smuzhiyun		                              <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */
197*4882a593Smuzhiyun		                              <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun		s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */
200*4882a593Smuzhiyun		                             <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */
201*4882a593Smuzhiyun		                             <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun		/*
204*4882a593Smuzhiyun		 * The following arrays of DVS voltages are not used, since we are
205*4882a593Smuzhiyun		 * not using GPIOs to control PMIC bucks, but they must be defined
206*4882a593Smuzhiyun		 * to please the driver.
207*4882a593Smuzhiyun		 */
208*4882a593Smuzhiyun		s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>,
209*4882a593Smuzhiyun		                                 <1250000>, <1200000>,
210*4882a593Smuzhiyun		                                 <1150000>, <1100000>,
211*4882a593Smuzhiyun		                                 <1000000>, <950000>;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun		s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
214*4882a593Smuzhiyun		                                 <1100000>, <1100000>,
215*4882a593Smuzhiyun		                                 <1000000>, <1000000>,
216*4882a593Smuzhiyun		                                 <1000000>, <1000000>;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun		s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
219*4882a593Smuzhiyun		                                 <1200000>, <1200000>,
220*4882a593Smuzhiyun		                                 <1200000>, <1200000>,
221*4882a593Smuzhiyun		                                 <1200000>, <1200000>;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun		clocks {
224*4882a593Smuzhiyun			compatible = "samsung,s5m8767-clk";
225*4882a593Smuzhiyun			#clock-cells = <1>;
226*4882a593Smuzhiyun			clock-output-names = "en32khz_ap",
227*4882a593Smuzhiyun			                     "en32khz_cp",
228*4882a593Smuzhiyun			                     "en32khz_bt";
229*4882a593Smuzhiyun		};
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun		regulators {
232*4882a593Smuzhiyun			ldo4_reg: LDO4 {
233*4882a593Smuzhiyun				regulator-name = "P1.0V_LDO_OUT4";
234*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
235*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
236*4882a593Smuzhiyun				regulator-always-on;
237*4882a593Smuzhiyun				op_mode = <0>;
238*4882a593Smuzhiyun			};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun			ldo5_reg: LDO5 {
241*4882a593Smuzhiyun				regulator-name = "P1.8V_LDO_OUT5";
242*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
243*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
244*4882a593Smuzhiyun				regulator-always-on;
245*4882a593Smuzhiyun				op_mode = <0>;
246*4882a593Smuzhiyun			};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun			ldo6_reg: LDO6 {
249*4882a593Smuzhiyun				regulator-name = "vdd_mydp";
250*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
251*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
252*4882a593Smuzhiyun				regulator-always-on;
253*4882a593Smuzhiyun				op_mode = <3>;
254*4882a593Smuzhiyun			};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun			ldo7_reg: LDO7 {
257*4882a593Smuzhiyun				regulator-name = "P1.1V_LDO_OUT7";
258*4882a593Smuzhiyun				regulator-min-microvolt = <1100000>;
259*4882a593Smuzhiyun				regulator-max-microvolt = <1100000>;
260*4882a593Smuzhiyun				regulator-always-on;
261*4882a593Smuzhiyun				op_mode = <3>;
262*4882a593Smuzhiyun			};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun			ldo8_reg: LDO8 {
265*4882a593Smuzhiyun				regulator-name = "P1.0V_LDO_OUT8";
266*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
267*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
268*4882a593Smuzhiyun				regulator-always-on;
269*4882a593Smuzhiyun				op_mode = <3>;
270*4882a593Smuzhiyun			};
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun			ldo10_reg: LDO10 {
273*4882a593Smuzhiyun				regulator-name = "P1.8V_LDO_OUT10";
274*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
275*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
276*4882a593Smuzhiyun				regulator-always-on;
277*4882a593Smuzhiyun				op_mode = <3>;
278*4882a593Smuzhiyun			};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun			ldo11_reg: LDO11 {
281*4882a593Smuzhiyun				regulator-name = "P1.8V_LDO_OUT11";
282*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
283*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
284*4882a593Smuzhiyun				regulator-always-on;
285*4882a593Smuzhiyun				op_mode = <0>;
286*4882a593Smuzhiyun			};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun			ldo12_reg: LDO12 {
289*4882a593Smuzhiyun				regulator-name = "P3.0V_LDO_OUT12";
290*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
291*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
292*4882a593Smuzhiyun				regulator-always-on;
293*4882a593Smuzhiyun				op_mode = <3>;
294*4882a593Smuzhiyun			};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun			ldo13_reg: LDO13 {
297*4882a593Smuzhiyun				regulator-name = "P1.8V_LDO_OUT13";
298*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
299*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
300*4882a593Smuzhiyun				regulator-always-on;
301*4882a593Smuzhiyun				op_mode = <0>;
302*4882a593Smuzhiyun			};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun			ldo14_reg: LDO14 {
305*4882a593Smuzhiyun				regulator-name = "P1.8V_LDO_OUT14";
306*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
307*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
308*4882a593Smuzhiyun				regulator-always-on;
309*4882a593Smuzhiyun				op_mode = <3>;
310*4882a593Smuzhiyun			};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun			ldo15_reg: LDO15 {
313*4882a593Smuzhiyun				regulator-name = "P1.0V_LDO_OUT15";
314*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
315*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
316*4882a593Smuzhiyun				regulator-always-on;
317*4882a593Smuzhiyun				op_mode = <3>;
318*4882a593Smuzhiyun			};
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun			ldo16_reg: LDO16 {
321*4882a593Smuzhiyun				regulator-name = "P1.8V_LDO_OUT16";
322*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
323*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
324*4882a593Smuzhiyun				regulator-always-on;
325*4882a593Smuzhiyun				op_mode = <3>;
326*4882a593Smuzhiyun			};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun			ldo17_reg: LDO17 {
329*4882a593Smuzhiyun				regulator-name = "P1.2V_LDO_OUT17";
330*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
331*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
332*4882a593Smuzhiyun				regulator-always-on;
333*4882a593Smuzhiyun				op_mode = <0>;
334*4882a593Smuzhiyun			};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun			ldo25_reg: LDO25 {
337*4882a593Smuzhiyun				regulator-name = "vdd_bridge";
338*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
339*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
340*4882a593Smuzhiyun				regulator-always-on;
341*4882a593Smuzhiyun				op_mode = <1>;
342*4882a593Smuzhiyun			};
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun			buck1_reg: BUCK1 {
345*4882a593Smuzhiyun				regulator-name = "vdd_mif";
346*4882a593Smuzhiyun				regulator-min-microvolt = <950000>;
347*4882a593Smuzhiyun				regulator-max-microvolt = <1300000>;
348*4882a593Smuzhiyun				regulator-always-on;
349*4882a593Smuzhiyun				regulator-boot-on;
350*4882a593Smuzhiyun				op_mode = <3>;
351*4882a593Smuzhiyun			};
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun			buck2_reg: BUCK2 {
354*4882a593Smuzhiyun				regulator-name = "vdd_arm";
355*4882a593Smuzhiyun				regulator-min-microvolt = <850000>;
356*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
357*4882a593Smuzhiyun				regulator-always-on;
358*4882a593Smuzhiyun				regulator-boot-on;
359*4882a593Smuzhiyun				op_mode = <3>;
360*4882a593Smuzhiyun			};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun			buck3_reg: BUCK3 {
363*4882a593Smuzhiyun				regulator-name = "vdd_int";
364*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
365*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
366*4882a593Smuzhiyun				regulator-always-on;
367*4882a593Smuzhiyun				regulator-boot-on;
368*4882a593Smuzhiyun				op_mode = <3>;
369*4882a593Smuzhiyun			};
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun			buck4_reg: BUCK4 {
372*4882a593Smuzhiyun				regulator-name = "vdd_g3d";
373*4882a593Smuzhiyun				regulator-min-microvolt = <850000>;
374*4882a593Smuzhiyun				regulator-max-microvolt = <1300000>;
375*4882a593Smuzhiyun				regulator-boot-on;
376*4882a593Smuzhiyun				op_mode = <3>;
377*4882a593Smuzhiyun			};
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun			buck5_reg: BUCK5 {
380*4882a593Smuzhiyun				regulator-name = "P1.8V_BUCK_OUT5";
381*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
382*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
383*4882a593Smuzhiyun				regulator-always-on;
384*4882a593Smuzhiyun				regulator-boot-on;
385*4882a593Smuzhiyun				op_mode = <1>;
386*4882a593Smuzhiyun			};
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun			buck6_reg: BUCK6 {
389*4882a593Smuzhiyun				regulator-name = "P1.2V_BUCK_OUT6";
390*4882a593Smuzhiyun				regulator-min-microvolt = <2050000>;
391*4882a593Smuzhiyun				regulator-max-microvolt = <2050000>;
392*4882a593Smuzhiyun				regulator-always-on;
393*4882a593Smuzhiyun				regulator-boot-on;
394*4882a593Smuzhiyun				op_mode = <0>;
395*4882a593Smuzhiyun			};
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun			buck9_reg: BUCK9 {
398*4882a593Smuzhiyun				regulator-name = "vdd_ummc";
399*4882a593Smuzhiyun				regulator-min-microvolt = <950000>;
400*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
401*4882a593Smuzhiyun				regulator-always-on;
402*4882a593Smuzhiyun				regulator-boot-on;
403*4882a593Smuzhiyun				op_mode = <3>;
404*4882a593Smuzhiyun			};
405*4882a593Smuzhiyun		};
406*4882a593Smuzhiyun	};
407*4882a593Smuzhiyun};
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun&dp {
410*4882a593Smuzhiyun	status = "okay";
411*4882a593Smuzhiyun	samsung,color-space = <0>;
412*4882a593Smuzhiyun	samsung,dynamic-range = <0>;
413*4882a593Smuzhiyun	samsung,ycbcr-coeff = <0>;
414*4882a593Smuzhiyun	samsung,color-depth = <1>;
415*4882a593Smuzhiyun	samsung,link-rate = <0x0a>;
416*4882a593Smuzhiyun	samsung,lane-count = <1>;
417*4882a593Smuzhiyun	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun	ports {
420*4882a593Smuzhiyun		port@0 {
421*4882a593Smuzhiyun			dp_out: endpoint {
422*4882a593Smuzhiyun				remote-endpoint = <&bridge_in>;
423*4882a593Smuzhiyun			};
424*4882a593Smuzhiyun		};
425*4882a593Smuzhiyun	};
426*4882a593Smuzhiyun};
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun&i2c_1 {
429*4882a593Smuzhiyun	status = "okay";
430*4882a593Smuzhiyun	samsung,i2c-sda-delay = <100>;
431*4882a593Smuzhiyun	samsung,i2c-max-bus-freq = <378000>;
432*4882a593Smuzhiyun};
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun&i2c_2 {
435*4882a593Smuzhiyun	status = "okay";
436*4882a593Smuzhiyun	samsung,i2c-sda-delay = <100>;
437*4882a593Smuzhiyun	samsung,i2c-max-bus-freq = <66000>;
438*4882a593Smuzhiyun};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun&i2c_3 {
441*4882a593Smuzhiyun	status = "okay";
442*4882a593Smuzhiyun	samsung,i2c-sda-delay = <100>;
443*4882a593Smuzhiyun	samsung,i2c-max-bus-freq = <66000>;
444*4882a593Smuzhiyun};
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun&i2c_4 {
447*4882a593Smuzhiyun	status = "okay";
448*4882a593Smuzhiyun	samsung,i2c-sda-delay = <100>;
449*4882a593Smuzhiyun	samsung,i2c-max-bus-freq = <66000>;
450*4882a593Smuzhiyun	clock-frequency = <66000>;
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun	cros_ec: embedded-controller {
453*4882a593Smuzhiyun		compatible = "google,cros-ec-i2c";
454*4882a593Smuzhiyun		reg = <0x1e>;
455*4882a593Smuzhiyun		interrupts = <6 IRQ_TYPE_NONE>;
456*4882a593Smuzhiyun		interrupt-parent = <&gpx1>;
457*4882a593Smuzhiyun		wakeup-source;
458*4882a593Smuzhiyun		u-boot,i2c-offset-len = <0>;
459*4882a593Smuzhiyun		ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
460*4882a593Smuzhiyun		cros_ec_ldo_tunnel: cros-ec-ldo-tunnel {
461*4882a593Smuzhiyun			compatible = "google,cros-ec-ldo-tunnel";
462*4882a593Smuzhiyun			#address-cells = <1>;
463*4882a593Smuzhiyun			#size-cells = <0>;
464*4882a593Smuzhiyun			power-regulator {
465*4882a593Smuzhiyun				compatible = "ti,tps65090";
466*4882a593Smuzhiyun				reg = <0x48>;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun				regulators {
469*4882a593Smuzhiyun					dcdc1 {
470*4882a593Smuzhiyun						ti,enable-ext-control;
471*4882a593Smuzhiyun					};
472*4882a593Smuzhiyun					dcdc2 {
473*4882a593Smuzhiyun						ti,enable-ext-control;
474*4882a593Smuzhiyun					};
475*4882a593Smuzhiyun					dcdc3 {
476*4882a593Smuzhiyun						ti,enable-ext-control;
477*4882a593Smuzhiyun					};
478*4882a593Smuzhiyun					fet1: fet1 {
479*4882a593Smuzhiyun						regulator-name = "vcd_led";
480*4882a593Smuzhiyun						ti,overcurrent-wait = <3>;
481*4882a593Smuzhiyun					};
482*4882a593Smuzhiyun					tps65090_fet2: fet2 {
483*4882a593Smuzhiyun						regulator-name = "video_mid";
484*4882a593Smuzhiyun						regulator-always-on;
485*4882a593Smuzhiyun						ti,overcurrent-wait = <3>;
486*4882a593Smuzhiyun					};
487*4882a593Smuzhiyun					fet3 {
488*4882a593Smuzhiyun						regulator-name = "wwan_r";
489*4882a593Smuzhiyun						regulator-always-on;
490*4882a593Smuzhiyun						ti,overcurrent-wait = <3>;
491*4882a593Smuzhiyun					};
492*4882a593Smuzhiyun					fet4 {
493*4882a593Smuzhiyun						regulator-name = "sdcard";
494*4882a593Smuzhiyun						ti,overcurrent-wait = <3>;
495*4882a593Smuzhiyun					};
496*4882a593Smuzhiyun					fet5 {
497*4882a593Smuzhiyun						regulator-name = "camout";
498*4882a593Smuzhiyun						regulator-always-on;
499*4882a593Smuzhiyun						ti,overcurrent-wait = <3>;
500*4882a593Smuzhiyun					};
501*4882a593Smuzhiyun					fet6: fet6 {
502*4882a593Smuzhiyun						regulator-name = "lcd_vdd";
503*4882a593Smuzhiyun						ti,overcurrent-wait = <3>;
504*4882a593Smuzhiyun					};
505*4882a593Smuzhiyun					tps65090_fet7: fet7 {
506*4882a593Smuzhiyun						regulator-name = "video_mid_1a";
507*4882a593Smuzhiyun						regulator-always-on;
508*4882a593Smuzhiyun						ti,overcurrent-wait = <3>;
509*4882a593Smuzhiyun					};
510*4882a593Smuzhiyun					ldo1 {
511*4882a593Smuzhiyun					};
512*4882a593Smuzhiyun					ldo2 {
513*4882a593Smuzhiyun					};
514*4882a593Smuzhiyun				};
515*4882a593Smuzhiyun			};
516*4882a593Smuzhiyun		};
517*4882a593Smuzhiyun	};
518*4882a593Smuzhiyun};
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun&i2c_5 {
521*4882a593Smuzhiyun	status = "okay";
522*4882a593Smuzhiyun	samsung,i2c-sda-delay = <100>;
523*4882a593Smuzhiyun	samsung,i2c-max-bus-freq = <66000>;
524*4882a593Smuzhiyun};
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun&i2c_7 {
527*4882a593Smuzhiyun	status = "okay";
528*4882a593Smuzhiyun	samsung,i2c-sda-delay = <100>;
529*4882a593Smuzhiyun	samsung,i2c-max-bus-freq = <66000>;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun	ps8622-bridge@8 {
532*4882a593Smuzhiyun		compatible = "parade,ps8622";
533*4882a593Smuzhiyun		reg = <0x8>;
534*4882a593Smuzhiyun		sleep-gpios = <&gpc3 6 GPIO_ACTIVE_LOW>;
535*4882a593Smuzhiyun		reset-gpios = <&gpc3 1 GPIO_ACTIVE_LOW>;
536*4882a593Smuzhiyun		hotplug-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
537*4882a593Smuzhiyun		power-supply = <&ldo6_reg>;
538*4882a593Smuzhiyun		parade,regs = /bits/ 8 <
539*4882a593Smuzhiyun			0x02 0xa1 0x01 /* HPD low */
540*4882a593Smuzhiyun			/*
541*4882a593Smuzhiyun			 * SW setting: [1:0] SW output 1.2V voltage is
542*4882a593Smuzhiyun			 * lower to 96%
543*4882a593Smuzhiyun			 */
544*4882a593Smuzhiyun			0x04 0x14 0x01
545*4882a593Smuzhiyun			/* RCO SS setting: [5:4] = b01 0.5%, b10 1%, b11 1.5% */
546*4882a593Smuzhiyun			0x04 0xe3 0x20
547*4882a593Smuzhiyun			0x04 0xe2 0x80 /* [7] RCO SS enable */
548*4882a593Smuzhiyun			/*
549*4882a593Smuzhiyun			 * RPHY Setting: [3:2] CDR tune wait cycle before
550*4882a593Smuzhiyun			 * measure for fine tune b00: 1us,
551*4882a593Smuzhiyun			 * 01: 0.5us, 10:2us, 11:4us
552*4882a593Smuzhiyun			 */
553*4882a593Smuzhiyun			0x04 0x8a 0x0c
554*4882a593Smuzhiyun			0x04 0x89 0x08 /* [3] RFD always on */
555*4882a593Smuzhiyun			/*
556*4882a593Smuzhiyun			 * CTN lock in/out: 20000ppm/80000ppm. Lock out 2 times
557*4882a593Smuzhiyun			 */
558*4882a593Smuzhiyun			0x04 0x71 0x2d
559*4882a593Smuzhiyun			/* 2.7G CDR settings */
560*4882a593Smuzhiyun			0x04 0x7d 0x07 /* NOF=40LSB for HBR CDR setting */
561*4882a593Smuzhiyun			0x04 0x7b 0x00 /* [1:0] Fmin=+4bands */
562*4882a593Smuzhiyun			0x04 0x7a 0xfd /* [7:5] DCO_FTRNG=+-40% */
563*4882a593Smuzhiyun			/*
564*4882a593Smuzhiyun			 * 1.62G CDR settings:
565*4882a593Smuzhiyun			 * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
566*4882a593Smuzhiyun			 */
567*4882a593Smuzhiyun			0x04 0xc0 0x12
568*4882a593Smuzhiyun			0x04 0xc1 0x92 /* Gitune=-37% */
569*4882a593Smuzhiyun			0x04 0xc2 0x1c /* Fbstep=100% */
570*4882a593Smuzhiyun			0x04 0x32 0x80 /* [7] LOS signal disable */
571*4882a593Smuzhiyun			/* RPIO Setting */
572*4882a593Smuzhiyun			/* [7:4] LVDS driver bias current 75% (250mV swing) */
573*4882a593Smuzhiyun			0x04 0x00 0xb0
574*4882a593Smuzhiyun			 /* [7:6] Right-bar GPIO output strength is 8mA */
575*4882a593Smuzhiyun			0x04 0x15 0x40
576*4882a593Smuzhiyun			/* EQ Training State Machine Setting */
577*4882a593Smuzhiyun			0x04 0x54 0x10 /* RCO calibration start */
578*4882a593Smuzhiyun			/* [4:0] MAX_LANE_COUNT set to one lane */
579*4882a593Smuzhiyun			0x01 0x02 0x81
580*4882a593Smuzhiyun			/* [4:0] LANE_COUNT_SET set to one lane */
581*4882a593Smuzhiyun			0x01 0x21 0x81
582*4882a593Smuzhiyun			0x00 0x52 0x20
583*4882a593Smuzhiyun			0x00 0xf1 0x03 /* HPD CP toggle enable */
584*4882a593Smuzhiyun			0x00 0x62 0x41
585*4882a593Smuzhiyun			/* Counter number add 1ms counter delay */
586*4882a593Smuzhiyun			0x00 0xf6 0x01
587*4882a593Smuzhiyun			/*
588*4882a593Smuzhiyun			 * [6]PWM function control by DPCD0040f[7], default
589*4882a593Smuzhiyun			 * is PWM block always works
590*4882a593Smuzhiyun			 */
591*4882a593Smuzhiyun			0x00 0x77 0x06
592*4882a593Smuzhiyun			0x00 0x4c 0x04
593*4882a593Smuzhiyun			/*
594*4882a593Smuzhiyun			 * 04h Adjust VTotal tolerance to fix the 30Hz no-
595*4882a593Smuzhiyun			 * display issue
596*4882a593Smuzhiyun			 * DPCD00400='h00 Parade OUI = 'h001cf8
597*4882a593Smuzhiyun			 */
598*4882a593Smuzhiyun			0x01 0xc0 0x00
599*4882a593Smuzhiyun			0x01 0xc1 0x1c /* DPCD00401='h1c */
600*4882a593Smuzhiyun			0x01 0xc2 0xf8 /* DPCD00402='hf8 */
601*4882a593Smuzhiyun			/* DPCD403~408 = ASCII code D2SLV5='h4432534c5635 */
602*4882a593Smuzhiyun			0x01 0xc3 0x44
603*4882a593Smuzhiyun			0x01 0xc4 0x32 /* DPCD404 */
604*4882a593Smuzhiyun			0x01 0xc5 0x53 /* DPCD405 */
605*4882a593Smuzhiyun			0x01 0xc6 0x4c /* DPCD406 */
606*4882a593Smuzhiyun			0x01 0xc7 0x56 /* DPCD407 */
607*4882a593Smuzhiyun			0x01 0xc8 0x35 /* DPCD408 */
608*4882a593Smuzhiyun			/* DPCD40A Initial Code major revision '01' */
609*4882a593Smuzhiyun			0x01 0xca 0x01
610*4882a593Smuzhiyun			/* DPCD40B Initial Code minor revision '05' */
611*4882a593Smuzhiyun			0x01 0xcb 0x05
612*4882a593Smuzhiyun			0x01 0xa5 0xa0 /* DPCD720, Select internal PWM */
613*4882a593Smuzhiyun			/*
614*4882a593Smuzhiyun			 * 0xff for 100% PWM of brightness, 0h for 0% brightness
615*4882a593Smuzhiyun			 */
616*4882a593Smuzhiyun			0x01 0xa7 0x00
617*4882a593Smuzhiyun			/*
618*4882a593Smuzhiyun			 * Set LVDS output as 6bit-VESA mapping, single LVDS
619*4882a593Smuzhiyun			 * channel
620*4882a593Smuzhiyun			 */
621*4882a593Smuzhiyun			0x01 0xcc 0x13
622*4882a593Smuzhiyun			0x02 0xb1 0x20 /* Enable SSC set by register */
623*4882a593Smuzhiyun			/* Set SSC enabled and +/-1% central spreading */
624*4882a593Smuzhiyun			0x04 0x10 0x16
625*4882a593Smuzhiyun			0x04 0x59 0x60 /* MPU Clock source: LC => RCO */
626*4882a593Smuzhiyun			0x04 0x54 0x14 /* LC -> RCO */
627*4882a593Smuzhiyun			0x02 0xa1 0x91>; /* HPD high */
628*4882a593Smuzhiyun		ports {
629*4882a593Smuzhiyun			port@0 {
630*4882a593Smuzhiyun				bridge_out: endpoint {
631*4882a593Smuzhiyun					remote-endpoint = <&panel_in>;
632*4882a593Smuzhiyun				};
633*4882a593Smuzhiyun			};
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun			port@1 {
636*4882a593Smuzhiyun				bridge_in: endpoint {
637*4882a593Smuzhiyun					remote-endpoint = <&dp_out>;
638*4882a593Smuzhiyun				};
639*4882a593Smuzhiyun			};
640*4882a593Smuzhiyun		};
641*4882a593Smuzhiyun	};
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun	soundcodec@20 {
644*4882a593Smuzhiyun		reg = <0x20>;
645*4882a593Smuzhiyun		compatible = "maxim,max98088-codec";
646*4882a593Smuzhiyun	};
647*4882a593Smuzhiyun};
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun#include "cros-ec-keyboard.dtsi"
650