1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * U-Boot additions to enable a generic Exynos GPIO driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2014 Google, Inc 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/{ 10*4882a593Smuzhiyun pinctrl_0: pinctrl@11400000 { 11*4882a593Smuzhiyun #address-cells = <1>; 12*4882a593Smuzhiyun #size-cells = <1>; 13*4882a593Smuzhiyun gpc4: gpc4 { 14*4882a593Smuzhiyun reg = <0x2e0 0x20>; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun gpx0: gpx0 { 17*4882a593Smuzhiyun reg = <0xc00 0x20>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun pinctrl_1: pinctrl@13400000 { 22*4882a593Smuzhiyun #address-cells = <1>; 23*4882a593Smuzhiyun #size-cells = <1>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun pinctrl_2: pinctrl@10d10000 { 27*4882a593Smuzhiyun #address-cells = <1>; 28*4882a593Smuzhiyun #size-cells = <1>; 29*4882a593Smuzhiyun gpv2: gpv2 { 30*4882a593Smuzhiyun reg = <0x060 0x20>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun gpv4: gpv4 { 33*4882a593Smuzhiyun reg = <0xc0 0x20>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun pinctrl_3: pinctrl@03860000 { 38*4882a593Smuzhiyun #address-cells = <1>; 39*4882a593Smuzhiyun #size-cells = <1>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun}; 43