1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 6*4882a593Smuzhiyun * published by the Free Software Foundation. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun#include "dra72-evm-common.dtsi" 9*4882a593Smuzhiyun#include <dt-bindings/net/ti-dp83867.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "TI DRA722 Rev C EVM"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun memory@0 { 15*4882a593Smuzhiyun device_type = "memory"; 16*4882a593Smuzhiyun reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun}; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun&i2c1 { 21*4882a593Smuzhiyun tps65917: tps65917@58 { 22*4882a593Smuzhiyun reg = <0x58>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun#include "dra72-evm-tps65917.dtsi" 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun&ldo2_reg { 31*4882a593Smuzhiyun /* LDO2_OUT --> VDDA_1V8_PHY2 */ 32*4882a593Smuzhiyun regulator-always-on; 33*4882a593Smuzhiyun regulator-boot-on; 34*4882a593Smuzhiyun}; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun&hdmi { 37*4882a593Smuzhiyun vdda-supply = <&ldo2_reg>; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun&pcf_gpio_21 { 41*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 42*4882a593Smuzhiyun interrupts = <30 IRQ_TYPE_EDGE_FALLING>; 43*4882a593Smuzhiyun}; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun&mac { 46*4882a593Smuzhiyun mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, 47*4882a593Smuzhiyun <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ 48*4882a593Smuzhiyun <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ 49*4882a593Smuzhiyun dual_emac; 50*4882a593Smuzhiyun}; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun&cpsw_emac0 { 53*4882a593Smuzhiyun phy-handle = <&dp83867_0>; 54*4882a593Smuzhiyun phy-mode = "rgmii-id"; 55*4882a593Smuzhiyun dual_emac_res_vlan = <1>; 56*4882a593Smuzhiyun}; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun&cpsw_emac1 { 59*4882a593Smuzhiyun phy-handle = <&dp83867_1>; 60*4882a593Smuzhiyun phy-mode = "rgmii-id"; 61*4882a593Smuzhiyun dual_emac_res_vlan = <2>; 62*4882a593Smuzhiyun}; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun&davinci_mdio { 65*4882a593Smuzhiyun dp83867_0: ethernet-phy@2 { 66*4882a593Smuzhiyun reg = <2>; 67*4882a593Smuzhiyun ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 68*4882a593Smuzhiyun ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; 69*4882a593Smuzhiyun ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; 70*4882a593Smuzhiyun ti,min-output-impedance; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun dp83867_1: ethernet-phy@3 { 74*4882a593Smuzhiyun reg = <3>; 75*4882a593Smuzhiyun ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 76*4882a593Smuzhiyun ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; 77*4882a593Smuzhiyun ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; 78*4882a593Smuzhiyun ti,min-output-impedance; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun}; 81