xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/dm816x.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License
3*4882a593Smuzhiyun * version 2.  This program is licensed "as is" without any warranty of any
4*4882a593Smuzhiyun * kind, whether express or implied.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
8*4882a593Smuzhiyun#include <dt-bindings/pinctrl/omap.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	compatible = "ti,dm816";
12*4882a593Smuzhiyun	interrupt-parent = <&intc>;
13*4882a593Smuzhiyun	#address-cells = <1>;
14*4882a593Smuzhiyun	#size-cells = <1>;
15*4882a593Smuzhiyun	chosen { };
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	aliases {
18*4882a593Smuzhiyun		i2c0 = &i2c1;
19*4882a593Smuzhiyun		i2c1 = &i2c2;
20*4882a593Smuzhiyun		serial0 = &uart1;
21*4882a593Smuzhiyun		serial1 = &uart2;
22*4882a593Smuzhiyun		serial2 = &uart3;
23*4882a593Smuzhiyun		ethernet0 = &eth0;
24*4882a593Smuzhiyun		ethernet1 = &eth1;
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	cpus {
28*4882a593Smuzhiyun		#address-cells = <1>;
29*4882a593Smuzhiyun		#size-cells = <0>;
30*4882a593Smuzhiyun		cpu@0 {
31*4882a593Smuzhiyun			compatible = "arm,cortex-a8";
32*4882a593Smuzhiyun			device_type = "cpu";
33*4882a593Smuzhiyun			reg = <0>;
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	pmu {
38*4882a593Smuzhiyun		compatible = "arm,cortex-a8-pmu";
39*4882a593Smuzhiyun		interrupts = <3>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	/*
43*4882a593Smuzhiyun	 * The soc node represents the soc top level view. It is used for IPs
44*4882a593Smuzhiyun	 * that are not memory mapped in the MPU view or for the MPU itself.
45*4882a593Smuzhiyun	 */
46*4882a593Smuzhiyun	soc {
47*4882a593Smuzhiyun		compatible = "ti,omap-infra";
48*4882a593Smuzhiyun		mpu {
49*4882a593Smuzhiyun			compatible = "ti,omap3-mpu";
50*4882a593Smuzhiyun			ti,hwmods = "mpu";
51*4882a593Smuzhiyun		};
52*4882a593Smuzhiyun	};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	/*
55*4882a593Smuzhiyun	 * XXX: Use a flat representation of the dm816x interconnect.
56*4882a593Smuzhiyun	 * The real dm816x interconnect network is quite complex. Since
57*4882a593Smuzhiyun	 * it will not bring real advantage to represent that in DT
58*4882a593Smuzhiyun	 * for the moment, just use a fake OCP bus entry to represent
59*4882a593Smuzhiyun	 * the whole bus hierarchy.
60*4882a593Smuzhiyun	 */
61*4882a593Smuzhiyun	ocp {
62*4882a593Smuzhiyun		compatible = "simple-bus";
63*4882a593Smuzhiyun		reg = <0x44000000 0x10000>;
64*4882a593Smuzhiyun		interrupts = <9 10>;
65*4882a593Smuzhiyun		#address-cells = <1>;
66*4882a593Smuzhiyun		#size-cells = <1>;
67*4882a593Smuzhiyun		ranges;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun		prcm: prcm@48180000 {
70*4882a593Smuzhiyun			compatible = "ti,dm816-prcm";
71*4882a593Smuzhiyun			reg = <0x48180000 0x4000>;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun			prcm_clocks: clocks {
74*4882a593Smuzhiyun				#address-cells = <1>;
75*4882a593Smuzhiyun				#size-cells = <0>;
76*4882a593Smuzhiyun			};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun			prcm_clockdomains: clockdomains {
79*4882a593Smuzhiyun			};
80*4882a593Smuzhiyun		};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun		scrm: scrm@48140000 {
83*4882a593Smuzhiyun			compatible = "ti,dm816-scrm", "simple-bus";
84*4882a593Smuzhiyun			reg = <0x48140000 0x21000>;
85*4882a593Smuzhiyun			#address-cells = <1>;
86*4882a593Smuzhiyun			#size-cells = <1>;
87*4882a593Smuzhiyun			#pinctrl-cells = <1>;
88*4882a593Smuzhiyun			ranges = <0 0x48140000 0x21000>;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun			dm816x_pinmux: pinmux@800 {
91*4882a593Smuzhiyun				compatible = "pinctrl-single";
92*4882a593Smuzhiyun				reg = <0x800 0x50a>;
93*4882a593Smuzhiyun				#address-cells = <1>;
94*4882a593Smuzhiyun				#size-cells = <0>;
95*4882a593Smuzhiyun				#pinctrl-cells = <1>;
96*4882a593Smuzhiyun				pinctrl-single,register-width = <16>;
97*4882a593Smuzhiyun				pinctrl-single,function-mask = <0xf>;
98*4882a593Smuzhiyun			};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun			/* Device Configuration Registers */
101*4882a593Smuzhiyun			scm_conf: syscon@600 {
102*4882a593Smuzhiyun				compatible = "syscon", "simple-bus";
103*4882a593Smuzhiyun				reg = <0x600 0x110>;
104*4882a593Smuzhiyun				#address-cells = <1>;
105*4882a593Smuzhiyun				#size-cells = <1>;
106*4882a593Smuzhiyun				ranges = <0 0x600 0x110>;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun				usb_phy0: usb-phy@20 {
109*4882a593Smuzhiyun					compatible = "ti,dm8168-usb-phy";
110*4882a593Smuzhiyun					reg = <0x20 0x8>;
111*4882a593Smuzhiyun					reg-names = "phy";
112*4882a593Smuzhiyun					clocks = <&main_fapll 6>;
113*4882a593Smuzhiyun					clock-names = "refclk";
114*4882a593Smuzhiyun					#phy-cells = <0>;
115*4882a593Smuzhiyun					syscon = <&scm_conf>;
116*4882a593Smuzhiyun				};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun				usb_phy1: usb-phy@28 {
119*4882a593Smuzhiyun					compatible = "ti,dm8168-usb-phy";
120*4882a593Smuzhiyun					reg = <0x28 0x8>;
121*4882a593Smuzhiyun					reg-names = "phy";
122*4882a593Smuzhiyun					clocks = <&main_fapll 6>;
123*4882a593Smuzhiyun					clock-names = "refclk";
124*4882a593Smuzhiyun					#phy-cells = <0>;
125*4882a593Smuzhiyun					syscon = <&scm_conf>;
126*4882a593Smuzhiyun				};
127*4882a593Smuzhiyun			};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun			scrm_clocks: clocks {
130*4882a593Smuzhiyun				#address-cells = <1>;
131*4882a593Smuzhiyun				#size-cells = <0>;
132*4882a593Smuzhiyun			};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun			scrm_clockdomains: clockdomains {
135*4882a593Smuzhiyun			};
136*4882a593Smuzhiyun		};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun		edma: edma@49000000 {
139*4882a593Smuzhiyun			compatible = "ti,edma3";
140*4882a593Smuzhiyun			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
141*4882a593Smuzhiyun			reg =   <0x49000000 0x10000>,
142*4882a593Smuzhiyun			        <0x44e10f90 0x40>;
143*4882a593Smuzhiyun			interrupts = <12 13 14>;
144*4882a593Smuzhiyun			#dma-cells = <1>;
145*4882a593Smuzhiyun		};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun		elm: elm@48080000 {
148*4882a593Smuzhiyun			compatible = "ti,816-elm";
149*4882a593Smuzhiyun			ti,hwmods = "elm";
150*4882a593Smuzhiyun			reg = <0x48080000 0x2000>;
151*4882a593Smuzhiyun			interrupts = <4>;
152*4882a593Smuzhiyun		};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun		gpio1: gpio@48032000 {
155*4882a593Smuzhiyun			compatible = "ti,omap4-gpio";
156*4882a593Smuzhiyun			ti,hwmods = "gpio1";
157*4882a593Smuzhiyun			ti,gpio-always-on;
158*4882a593Smuzhiyun			reg = <0x48032000 0x1000>;
159*4882a593Smuzhiyun			interrupts = <96>;
160*4882a593Smuzhiyun			gpio-controller;
161*4882a593Smuzhiyun			#gpio-cells = <2>;
162*4882a593Smuzhiyun			interrupt-controller;
163*4882a593Smuzhiyun			#interrupt-cells = <2>;
164*4882a593Smuzhiyun		};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun		gpio2: gpio@4804c000 {
167*4882a593Smuzhiyun			compatible = "ti,omap4-gpio";
168*4882a593Smuzhiyun			ti,hwmods = "gpio2";
169*4882a593Smuzhiyun			ti,gpio-always-on;
170*4882a593Smuzhiyun			reg = <0x4804c000 0x1000>;
171*4882a593Smuzhiyun			interrupts = <98>;
172*4882a593Smuzhiyun			gpio-controller;
173*4882a593Smuzhiyun			#gpio-cells = <2>;
174*4882a593Smuzhiyun			interrupt-controller;
175*4882a593Smuzhiyun			#interrupt-cells = <2>;
176*4882a593Smuzhiyun		};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun		gpmc: gpmc@50000000 {
179*4882a593Smuzhiyun			compatible = "ti,am3352-gpmc";
180*4882a593Smuzhiyun			ti,hwmods = "gpmc";
181*4882a593Smuzhiyun			reg = <0x50000000 0x2000>;
182*4882a593Smuzhiyun			#address-cells = <2>;
183*4882a593Smuzhiyun			#size-cells = <1>;
184*4882a593Smuzhiyun			interrupts = <100>;
185*4882a593Smuzhiyun			dmas = <&edma 52>;
186*4882a593Smuzhiyun			dma-names = "rxtx";
187*4882a593Smuzhiyun			gpmc,num-cs = <6>;
188*4882a593Smuzhiyun			gpmc,num-waitpins = <2>;
189*4882a593Smuzhiyun			interrupt-controller;
190*4882a593Smuzhiyun			#interrupt-cells = <2>;
191*4882a593Smuzhiyun			gpio-controller;
192*4882a593Smuzhiyun			#gpio-cells = <2>;
193*4882a593Smuzhiyun		};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun		i2c1: i2c@48028000 {
196*4882a593Smuzhiyun			compatible = "ti,omap4-i2c";
197*4882a593Smuzhiyun			ti,hwmods = "i2c1";
198*4882a593Smuzhiyun			reg = <0x48028000 0x1000>;
199*4882a593Smuzhiyun			#address-cells = <1>;
200*4882a593Smuzhiyun			#size-cells = <0>;
201*4882a593Smuzhiyun			interrupts = <70>;
202*4882a593Smuzhiyun			dmas = <&edma 58 &edma 59>;
203*4882a593Smuzhiyun			dma-names = "tx", "rx";
204*4882a593Smuzhiyun		};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun		i2c2: i2c@4802a000 {
207*4882a593Smuzhiyun			compatible = "ti,omap4-i2c";
208*4882a593Smuzhiyun			ti,hwmods = "i2c2";
209*4882a593Smuzhiyun			reg = <0x4802a000 0x1000>;
210*4882a593Smuzhiyun			#address-cells = <1>;
211*4882a593Smuzhiyun			#size-cells = <0>;
212*4882a593Smuzhiyun			interrupts = <71>;
213*4882a593Smuzhiyun			dmas = <&edma 60 &edma 61>;
214*4882a593Smuzhiyun			dma-names = "tx", "rx";
215*4882a593Smuzhiyun		};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun		intc: interrupt-controller@48200000 {
218*4882a593Smuzhiyun			compatible = "ti,dm816-intc";
219*4882a593Smuzhiyun			interrupt-controller;
220*4882a593Smuzhiyun			#interrupt-cells = <1>;
221*4882a593Smuzhiyun			reg = <0x48200000 0x1000>;
222*4882a593Smuzhiyun		};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun		rtc: rtc@480c0000 {
225*4882a593Smuzhiyun			compatible = "ti,am3352-rtc", "ti,da830-rtc";
226*4882a593Smuzhiyun			reg = <0x480c0000 0x1000>;
227*4882a593Smuzhiyun			interrupts = <75 76>;
228*4882a593Smuzhiyun			ti,hwmods = "rtc";
229*4882a593Smuzhiyun		};
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun		mailbox: mailbox@480c8000 {
232*4882a593Smuzhiyun			compatible = "ti,omap4-mailbox";
233*4882a593Smuzhiyun			reg = <0x480c8000 0x2000>;
234*4882a593Smuzhiyun			interrupts = <77>;
235*4882a593Smuzhiyun			ti,hwmods = "mailbox";
236*4882a593Smuzhiyun			#mbox-cells = <1>;
237*4882a593Smuzhiyun			ti,mbox-num-users = <4>;
238*4882a593Smuzhiyun			ti,mbox-num-fifos = <12>;
239*4882a593Smuzhiyun			mbox_dsp: mbox_dsp {
240*4882a593Smuzhiyun				ti,mbox-tx = <3 0 0>;
241*4882a593Smuzhiyun				ti,mbox-rx = <0 0 0>;
242*4882a593Smuzhiyun			};
243*4882a593Smuzhiyun		};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun		spinbox: spinbox@480ca000 {
246*4882a593Smuzhiyun			compatible = "ti,omap4-hwspinlock";
247*4882a593Smuzhiyun			reg = <0x480ca000 0x2000>;
248*4882a593Smuzhiyun			ti,hwmods = "spinbox";
249*4882a593Smuzhiyun			#hwlock-cells = <1>;
250*4882a593Smuzhiyun		};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun		mdio: mdio@4a100800 {
253*4882a593Smuzhiyun			compatible = "ti,davinci_mdio";
254*4882a593Smuzhiyun			#address-cells = <1>;
255*4882a593Smuzhiyun			#size-cells = <0>;
256*4882a593Smuzhiyun			reg = <0x4a100800 0x100>;
257*4882a593Smuzhiyun			ti,hwmods = "davinci_mdio";
258*4882a593Smuzhiyun			bus_freq = <1000000>;
259*4882a593Smuzhiyun			phy0: ethernet-phy@0 {
260*4882a593Smuzhiyun				reg = <1>;
261*4882a593Smuzhiyun			};
262*4882a593Smuzhiyun			phy1: ethernet-phy@1 {
263*4882a593Smuzhiyun				reg = <2>;
264*4882a593Smuzhiyun			};
265*4882a593Smuzhiyun		};
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun		eth0: ethernet@4a100000 {
268*4882a593Smuzhiyun			compatible = "ti,dm816-emac";
269*4882a593Smuzhiyun			ti,hwmods = "emac0";
270*4882a593Smuzhiyun			reg = <0x4a100000 0x800
271*4882a593Smuzhiyun			       0x4a100900 0x3700>;
272*4882a593Smuzhiyun			clocks = <&sysclk24_ck>;
273*4882a593Smuzhiyun			syscon = <&scm_conf>;
274*4882a593Smuzhiyun			ti,davinci-ctrl-reg-offset = <0>;
275*4882a593Smuzhiyun			ti,davinci-ctrl-mod-reg-offset = <0x900>;
276*4882a593Smuzhiyun			ti,davinci-ctrl-ram-offset = <0x2000>;
277*4882a593Smuzhiyun			ti,davinci-ctrl-ram-size = <0x2000>;
278*4882a593Smuzhiyun			interrupts = <40 41 42 43>;
279*4882a593Smuzhiyun			phy-handle = <&phy0>;
280*4882a593Smuzhiyun		};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun		eth1: ethernet@4a120000 {
283*4882a593Smuzhiyun			compatible = "ti,dm816-emac";
284*4882a593Smuzhiyun			ti,hwmods = "emac1";
285*4882a593Smuzhiyun			reg = <0x4a120000 0x4000>;
286*4882a593Smuzhiyun			clocks = <&sysclk24_ck>;
287*4882a593Smuzhiyun			syscon = <&scm_conf>;
288*4882a593Smuzhiyun			ti,davinci-ctrl-reg-offset = <0>;
289*4882a593Smuzhiyun			ti,davinci-ctrl-mod-reg-offset = <0x900>;
290*4882a593Smuzhiyun			ti,davinci-ctrl-ram-offset = <0x2000>;
291*4882a593Smuzhiyun			ti,davinci-ctrl-ram-size = <0x2000>;
292*4882a593Smuzhiyun			interrupts = <44 45 46 47>;
293*4882a593Smuzhiyun			phy-handle = <&phy1>;
294*4882a593Smuzhiyun		};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun		mcspi1: spi@48030000 {
297*4882a593Smuzhiyun			compatible = "ti,omap4-mcspi";
298*4882a593Smuzhiyun			reg = <0x48030000 0x1000>;
299*4882a593Smuzhiyun			#address-cells = <1>;
300*4882a593Smuzhiyun			#size-cells = <0>;
301*4882a593Smuzhiyun			interrupts = <65>;
302*4882a593Smuzhiyun			ti,spi-num-cs = <4>;
303*4882a593Smuzhiyun			ti,hwmods = "mcspi1";
304*4882a593Smuzhiyun			dmas = <&edma 16 &edma 17
305*4882a593Smuzhiyun				&edma 18 &edma 19
306*4882a593Smuzhiyun				&edma 20 &edma 21
307*4882a593Smuzhiyun				&edma 22 &edma 23>;
308*4882a593Smuzhiyun			dma-names = "tx0", "rx0", "tx1", "rx1",
309*4882a593Smuzhiyun				    "tx2", "rx2", "tx3", "rx3";
310*4882a593Smuzhiyun		};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun		mmc1: mmc@48060000 {
313*4882a593Smuzhiyun			compatible = "ti,omap4-hsmmc";
314*4882a593Smuzhiyun			reg = <0x48060000 0x11000>;
315*4882a593Smuzhiyun			ti,hwmods = "mmc1";
316*4882a593Smuzhiyun			interrupts = <64>;
317*4882a593Smuzhiyun			dmas = <&edma 24 &edma 25>;
318*4882a593Smuzhiyun			dma-names = "tx", "rx";
319*4882a593Smuzhiyun		};
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun		timer1: timer@4802e000 {
322*4882a593Smuzhiyun			compatible = "ti,dm816-timer";
323*4882a593Smuzhiyun			reg = <0x4802e000 0x2000>;
324*4882a593Smuzhiyun			interrupts = <67>;
325*4882a593Smuzhiyun			ti,hwmods = "timer1";
326*4882a593Smuzhiyun			ti,timer-alwon;
327*4882a593Smuzhiyun		};
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun		timer2: timer@48040000 {
330*4882a593Smuzhiyun			compatible = "ti,dm816-timer";
331*4882a593Smuzhiyun			reg = <0x48040000 0x2000>;
332*4882a593Smuzhiyun			interrupts = <68>;
333*4882a593Smuzhiyun			ti,hwmods = "timer2";
334*4882a593Smuzhiyun		};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun		timer3: timer@48042000 {
337*4882a593Smuzhiyun			compatible = "ti,dm816-timer";
338*4882a593Smuzhiyun			reg = <0x48042000 0x2000>;
339*4882a593Smuzhiyun			interrupts = <69>;
340*4882a593Smuzhiyun			ti,hwmods = "timer3";
341*4882a593Smuzhiyun		};
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun		timer4: timer@48044000 {
344*4882a593Smuzhiyun			compatible = "ti,dm816-timer";
345*4882a593Smuzhiyun			reg = <0x48044000 0x2000>;
346*4882a593Smuzhiyun			interrupts = <92>;
347*4882a593Smuzhiyun			ti,hwmods = "timer4";
348*4882a593Smuzhiyun			ti,timer-pwm;
349*4882a593Smuzhiyun		};
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun		timer5: timer@48046000 {
352*4882a593Smuzhiyun			compatible = "ti,dm816-timer";
353*4882a593Smuzhiyun			reg = <0x48046000 0x2000>;
354*4882a593Smuzhiyun			interrupts = <93>;
355*4882a593Smuzhiyun			ti,hwmods = "timer5";
356*4882a593Smuzhiyun			ti,timer-pwm;
357*4882a593Smuzhiyun		};
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun		timer6: timer@48048000 {
360*4882a593Smuzhiyun			compatible = "ti,dm816-timer";
361*4882a593Smuzhiyun			reg = <0x48048000 0x2000>;
362*4882a593Smuzhiyun			interrupts = <94>;
363*4882a593Smuzhiyun			ti,hwmods = "timer6";
364*4882a593Smuzhiyun			ti,timer-pwm;
365*4882a593Smuzhiyun		};
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun		timer7: timer@4804a000 {
368*4882a593Smuzhiyun			compatible = "ti,dm816-timer";
369*4882a593Smuzhiyun			reg = <0x4804a000 0x2000>;
370*4882a593Smuzhiyun			interrupts = <95>;
371*4882a593Smuzhiyun			ti,hwmods = "timer7";
372*4882a593Smuzhiyun			ti,timer-pwm;
373*4882a593Smuzhiyun		};
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun		uart1: uart@48020000 {
376*4882a593Smuzhiyun			compatible = "ti,am3352-uart", "ti,omap3-uart";
377*4882a593Smuzhiyun			ti,hwmods = "uart1";
378*4882a593Smuzhiyun			reg = <0x48020000 0x2000>;
379*4882a593Smuzhiyun			clock-frequency = <48000000>;
380*4882a593Smuzhiyun			interrupts = <72>;
381*4882a593Smuzhiyun			dmas = <&edma 26 &edma 27>;
382*4882a593Smuzhiyun			dma-names = "tx", "rx";
383*4882a593Smuzhiyun		};
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun		uart2: uart@48022000 {
386*4882a593Smuzhiyun			compatible = "ti,am3352-uart", "ti,omap3-uart";
387*4882a593Smuzhiyun			ti,hwmods = "uart2";
388*4882a593Smuzhiyun			reg = <0x48022000 0x2000>;
389*4882a593Smuzhiyun			clock-frequency = <48000000>;
390*4882a593Smuzhiyun			interrupts = <73>;
391*4882a593Smuzhiyun			dmas = <&edma 28 &edma 29>;
392*4882a593Smuzhiyun			dma-names = "tx", "rx";
393*4882a593Smuzhiyun		};
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun		uart3: uart@48024000 {
396*4882a593Smuzhiyun			compatible = "ti,am3352-uart", "ti,omap3-uart";
397*4882a593Smuzhiyun			ti,hwmods = "uart3";
398*4882a593Smuzhiyun			reg = <0x48024000 0x2000>;
399*4882a593Smuzhiyun			clock-frequency = <48000000>;
400*4882a593Smuzhiyun			interrupts = <74>;
401*4882a593Smuzhiyun			dmas = <&edma 30 &edma 31>;
402*4882a593Smuzhiyun			dma-names = "tx", "rx";
403*4882a593Smuzhiyun		};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun		/* NOTE: USB needs a transceiver driver for phys to work */
406*4882a593Smuzhiyun		usb: usb_otg_hs@47401000 {
407*4882a593Smuzhiyun			compatible = "ti,am33xx-usb";
408*4882a593Smuzhiyun			reg = <0x47401000 0x400000>;
409*4882a593Smuzhiyun			ranges;
410*4882a593Smuzhiyun			#address-cells = <1>;
411*4882a593Smuzhiyun			#size-cells = <1>;
412*4882a593Smuzhiyun			ti,hwmods = "usb_otg_hs";
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun			usb0: usb@47401000 {
415*4882a593Smuzhiyun				compatible = "ti,musb-dm816";
416*4882a593Smuzhiyun				reg = <0x47401400 0x400
417*4882a593Smuzhiyun				       0x47401000 0x200>;
418*4882a593Smuzhiyun				reg-names = "mc", "control";
419*4882a593Smuzhiyun				interrupts = <18>;
420*4882a593Smuzhiyun				interrupt-names = "mc";
421*4882a593Smuzhiyun				dr_mode = "host";
422*4882a593Smuzhiyun				interface-type = <0>;
423*4882a593Smuzhiyun				phys = <&usb_phy0>;
424*4882a593Smuzhiyun				phy-names = "usb2-phy";
425*4882a593Smuzhiyun				mentor,multipoint = <1>;
426*4882a593Smuzhiyun				mentor,num-eps = <16>;
427*4882a593Smuzhiyun				mentor,ram-bits = <12>;
428*4882a593Smuzhiyun				mentor,power = <500>;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
431*4882a593Smuzhiyun					&cppi41dma  2 0 &cppi41dma  3 0
432*4882a593Smuzhiyun					&cppi41dma  4 0 &cppi41dma  5 0
433*4882a593Smuzhiyun					&cppi41dma  6 0 &cppi41dma  7 0
434*4882a593Smuzhiyun					&cppi41dma  8 0 &cppi41dma  9 0
435*4882a593Smuzhiyun					&cppi41dma 10 0 &cppi41dma 11 0
436*4882a593Smuzhiyun					&cppi41dma 12 0 &cppi41dma 13 0
437*4882a593Smuzhiyun					&cppi41dma 14 0 &cppi41dma  0 1
438*4882a593Smuzhiyun					&cppi41dma  1 1 &cppi41dma  2 1
439*4882a593Smuzhiyun					&cppi41dma  3 1 &cppi41dma  4 1
440*4882a593Smuzhiyun					&cppi41dma  5 1 &cppi41dma  6 1
441*4882a593Smuzhiyun					&cppi41dma  7 1 &cppi41dma  8 1
442*4882a593Smuzhiyun					&cppi41dma  9 1 &cppi41dma 10 1
443*4882a593Smuzhiyun					&cppi41dma 11 1 &cppi41dma 12 1
444*4882a593Smuzhiyun					&cppi41dma 13 1 &cppi41dma 14 1>;
445*4882a593Smuzhiyun				dma-names =
446*4882a593Smuzhiyun					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
447*4882a593Smuzhiyun					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
448*4882a593Smuzhiyun					"rx14", "rx15",
449*4882a593Smuzhiyun					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
450*4882a593Smuzhiyun					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
451*4882a593Smuzhiyun					"tx14", "tx15";
452*4882a593Smuzhiyun			};
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun			usb1: usb@47401800 {
455*4882a593Smuzhiyun				compatible = "ti,musb-dm816";
456*4882a593Smuzhiyun				reg = <0x47401c00 0x400
457*4882a593Smuzhiyun				       0x47401800 0x200>;
458*4882a593Smuzhiyun				reg-names = "mc", "control";
459*4882a593Smuzhiyun				interrupts = <19>;
460*4882a593Smuzhiyun				interrupt-names = "mc";
461*4882a593Smuzhiyun				dr_mode = "host";
462*4882a593Smuzhiyun				interface-type = <0>;
463*4882a593Smuzhiyun				phys = <&usb_phy1>;
464*4882a593Smuzhiyun				phy-names = "usb2-phy";
465*4882a593Smuzhiyun				mentor,multipoint = <1>;
466*4882a593Smuzhiyun				mentor,num-eps = <16>;
467*4882a593Smuzhiyun				mentor,ram-bits = <12>;
468*4882a593Smuzhiyun				mentor,power = <500>;
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
471*4882a593Smuzhiyun					&cppi41dma 17 0 &cppi41dma 18 0
472*4882a593Smuzhiyun					&cppi41dma 19 0 &cppi41dma 20 0
473*4882a593Smuzhiyun					&cppi41dma 21 0 &cppi41dma 22 0
474*4882a593Smuzhiyun					&cppi41dma 23 0 &cppi41dma 24 0
475*4882a593Smuzhiyun					&cppi41dma 25 0 &cppi41dma 26 0
476*4882a593Smuzhiyun					&cppi41dma 27 0 &cppi41dma 28 0
477*4882a593Smuzhiyun					&cppi41dma 29 0 &cppi41dma 15 1
478*4882a593Smuzhiyun					&cppi41dma 16 1 &cppi41dma 17 1
479*4882a593Smuzhiyun					&cppi41dma 18 1 &cppi41dma 19 1
480*4882a593Smuzhiyun					&cppi41dma 20 1 &cppi41dma 21 1
481*4882a593Smuzhiyun					&cppi41dma 22 1 &cppi41dma 23 1
482*4882a593Smuzhiyun					&cppi41dma 24 1 &cppi41dma 25 1
483*4882a593Smuzhiyun					&cppi41dma 26 1 &cppi41dma 27 1
484*4882a593Smuzhiyun					&cppi41dma 28 1 &cppi41dma 29 1>;
485*4882a593Smuzhiyun				dma-names =
486*4882a593Smuzhiyun					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
487*4882a593Smuzhiyun					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
488*4882a593Smuzhiyun					"rx14", "rx15",
489*4882a593Smuzhiyun					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
490*4882a593Smuzhiyun					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
491*4882a593Smuzhiyun					"tx14", "tx15";
492*4882a593Smuzhiyun			};
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun			cppi41dma: dma-controller@47402000 {
495*4882a593Smuzhiyun				compatible = "ti,am3359-cppi41";
496*4882a593Smuzhiyun				reg =  <0x47400000 0x1000
497*4882a593Smuzhiyun					0x47402000 0x1000
498*4882a593Smuzhiyun					0x47403000 0x1000
499*4882a593Smuzhiyun					0x47404000 0x4000>;
500*4882a593Smuzhiyun				reg-names = "glue", "controller", "scheduler", "queuemgr";
501*4882a593Smuzhiyun				interrupts = <17>;
502*4882a593Smuzhiyun				interrupt-names = "glue";
503*4882a593Smuzhiyun				#dma-cells = <2>;
504*4882a593Smuzhiyun				#dma-channels = <30>;
505*4882a593Smuzhiyun				#dma-requests = <256>;
506*4882a593Smuzhiyun			};
507*4882a593Smuzhiyun		};
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun		wd_timer2: wd_timer@480c2000 {
510*4882a593Smuzhiyun			compatible = "ti,omap3-wdt";
511*4882a593Smuzhiyun			ti,hwmods = "wd_timer";
512*4882a593Smuzhiyun			reg = <0x480c2000 0x1000>;
513*4882a593Smuzhiyun			interrupts = <0>;
514*4882a593Smuzhiyun		};
515*4882a593Smuzhiyun	};
516*4882a593Smuzhiyun};
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun#include "dm816x-clocks.dtsi"
519