1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 3*4882a593Smuzhiyun * 4 USART. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Licensed under GPLv2. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/at91.h> 11*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun aliases { 15*4882a593Smuzhiyun serial4 = &usart3; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun ahb { 19*4882a593Smuzhiyun apb { 20*4882a593Smuzhiyun pinctrl@fffff400 { 21*4882a593Smuzhiyun usart3 { 22*4882a593Smuzhiyun pinctrl_usart3: usart3-0 { 23*4882a593Smuzhiyun atmel,pins = 24*4882a593Smuzhiyun <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */ 25*4882a593Smuzhiyun AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */ 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun pinctrl_usart3_rts: usart3_rts-0 { 29*4882a593Smuzhiyun atmel,pins = 30*4882a593Smuzhiyun <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun pinctrl_usart3_cts: usart3_cts-0 { 34*4882a593Smuzhiyun atmel,pins = 35*4882a593Smuzhiyun <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun pinctrl_usart3_sck: usart3_sck-0 { 39*4882a593Smuzhiyun atmel,pins = 40*4882a593Smuzhiyun <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */ 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun pmc: pmc@fffffc00 { 46*4882a593Smuzhiyun periphck { 47*4882a593Smuzhiyun usart3_clk: usart3_clk@8 { 48*4882a593Smuzhiyun #clock-cells = <0>; 49*4882a593Smuzhiyun reg = <8>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun usart3: serial@f8028000 { 55*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 56*4882a593Smuzhiyun reg = <0xf8028000 0x200>; 57*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 58*4882a593Smuzhiyun pinctrl-names = "default"; 59*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usart3>; 60*4882a593Smuzhiyun dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>, 61*4882a593Smuzhiyun <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 62*4882a593Smuzhiyun dma-names = "tx", "rx"; 63*4882a593Smuzhiyun clocks = <&usart3_clk>; 64*4882a593Smuzhiyun clock-names = "usart"; 65*4882a593Smuzhiyun status = "disabled"; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70