xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/at91sam9x5_lcd.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
3*4882a593Smuzhiyun * LCD controller.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Licensed under GPLv2.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/at91.h>
11*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	ahb {
15*4882a593Smuzhiyun		apb {
16*4882a593Smuzhiyun			hlcdc: hlcdc@f8038000 {
17*4882a593Smuzhiyun				compatible = "atmel,at91sam9x5-hlcdc";
18*4882a593Smuzhiyun				reg = <0xf8038000 0x4000>;
19*4882a593Smuzhiyun				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
20*4882a593Smuzhiyun				clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
21*4882a593Smuzhiyun				clock-names = "periph_clk","sys_clk", "slow_clk";
22*4882a593Smuzhiyun				status = "disabled";
23*4882a593Smuzhiyun			};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun			pinctrl@fffff400 {
26*4882a593Smuzhiyun				lcd {
27*4882a593Smuzhiyun					pinctrl_lcd_base: lcd-base-0 {
28*4882a593Smuzhiyun						atmel,pins =
29*4882a593Smuzhiyun							<AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDVSYNC */
30*4882a593Smuzhiyun							 AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDHSYNC */
31*4882a593Smuzhiyun							 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDDISP */
32*4882a593Smuzhiyun							 AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDDEN */
33*4882a593Smuzhiyun							 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDPCK */
34*4882a593Smuzhiyun					};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun					pinctrl_lcd_pwm: lcd-pwm-0 {
37*4882a593Smuzhiyun						atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDPWM */
38*4882a593Smuzhiyun					};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun					pinctrl_lcd_rgb444: lcd-rgb-0 {
41*4882a593Smuzhiyun						atmel,pins =
42*4882a593Smuzhiyun							<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
43*4882a593Smuzhiyun							 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
44*4882a593Smuzhiyun							 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
45*4882a593Smuzhiyun							 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
46*4882a593Smuzhiyun							 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
47*4882a593Smuzhiyun							 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
48*4882a593Smuzhiyun							 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
49*4882a593Smuzhiyun							 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
50*4882a593Smuzhiyun							 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
51*4882a593Smuzhiyun							 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
52*4882a593Smuzhiyun							 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
53*4882a593Smuzhiyun							 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD11 pin */
54*4882a593Smuzhiyun					};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun					pinctrl_lcd_rgb565: lcd-rgb-1 {
57*4882a593Smuzhiyun						atmel,pins =
58*4882a593Smuzhiyun							<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
59*4882a593Smuzhiyun							 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
60*4882a593Smuzhiyun							 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
61*4882a593Smuzhiyun							 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
62*4882a593Smuzhiyun							 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
63*4882a593Smuzhiyun							 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
64*4882a593Smuzhiyun							 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
65*4882a593Smuzhiyun							 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
66*4882a593Smuzhiyun							 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
67*4882a593Smuzhiyun							 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
68*4882a593Smuzhiyun							 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
69*4882a593Smuzhiyun							 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
70*4882a593Smuzhiyun							 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
71*4882a593Smuzhiyun							 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
72*4882a593Smuzhiyun							 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
73*4882a593Smuzhiyun							 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD15 pin */
74*4882a593Smuzhiyun					};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun					pinctrl_lcd_rgb666: lcd-rgb-2 {
77*4882a593Smuzhiyun						atmel,pins =
78*4882a593Smuzhiyun							<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
79*4882a593Smuzhiyun							 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
80*4882a593Smuzhiyun							 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
81*4882a593Smuzhiyun							 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
82*4882a593Smuzhiyun							 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
83*4882a593Smuzhiyun							 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
84*4882a593Smuzhiyun							 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
85*4882a593Smuzhiyun							 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
86*4882a593Smuzhiyun							 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
87*4882a593Smuzhiyun							 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
88*4882a593Smuzhiyun							 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
89*4882a593Smuzhiyun							 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
90*4882a593Smuzhiyun							 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
91*4882a593Smuzhiyun							 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
92*4882a593Smuzhiyun							 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
93*4882a593Smuzhiyun							 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD15 pin */
94*4882a593Smuzhiyun							 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD16 pin */
95*4882a593Smuzhiyun							 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD17 pin */
96*4882a593Smuzhiyun					};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun					pinctrl_lcd_rgb888: lcd-rgb-3 {
99*4882a593Smuzhiyun						atmel,pins =
100*4882a593Smuzhiyun							<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
101*4882a593Smuzhiyun							 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
102*4882a593Smuzhiyun							 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
103*4882a593Smuzhiyun							 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
104*4882a593Smuzhiyun							 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
105*4882a593Smuzhiyun							 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
106*4882a593Smuzhiyun							 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
107*4882a593Smuzhiyun							 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
108*4882a593Smuzhiyun							 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
109*4882a593Smuzhiyun							 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
110*4882a593Smuzhiyun							 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
111*4882a593Smuzhiyun							 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
112*4882a593Smuzhiyun							 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
113*4882a593Smuzhiyun							 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
114*4882a593Smuzhiyun							 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
115*4882a593Smuzhiyun							 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD15 pin */
116*4882a593Smuzhiyun							 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD16 pin */
117*4882a593Smuzhiyun							 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD17 pin */
118*4882a593Smuzhiyun							 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD18 pin */
119*4882a593Smuzhiyun							 AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD19 pin */
120*4882a593Smuzhiyun							 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD20 pin */
121*4882a593Smuzhiyun							 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD21 pin */
122*4882a593Smuzhiyun							 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD22 pin */
123*4882a593Smuzhiyun							 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD23 pin */
124*4882a593Smuzhiyun					};
125*4882a593Smuzhiyun				};
126*4882a593Smuzhiyun			};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun			pmc: pmc@fffffc00 {
129*4882a593Smuzhiyun				periphck {
130*4882a593Smuzhiyun					lcdc_clk: lcdc_clk@25 {
131*4882a593Smuzhiyun						#clock-cells = <0>;
132*4882a593Smuzhiyun						reg = <25>;
133*4882a593Smuzhiyun					};
134*4882a593Smuzhiyun				};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun				systemck {
137*4882a593Smuzhiyun					lcdck: lcdck@3 {
138*4882a593Smuzhiyun						#clock-cells = <0>;
139*4882a593Smuzhiyun						reg = <3>;
140*4882a593Smuzhiyun						clocks = <&mck>;
141*4882a593Smuzhiyun					};
142*4882a593Smuzhiyun				};
143*4882a593Smuzhiyun			};
144*4882a593Smuzhiyun		};
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun};
147