1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an 3*4882a593Smuzhiyun * Image Sensor Interface. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Licensed under GPLv2. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/at91.h> 11*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun ahb { 15*4882a593Smuzhiyun apb { 16*4882a593Smuzhiyun pinctrl@fffff400 { 17*4882a593Smuzhiyun isi { 18*4882a593Smuzhiyun pinctrl_isi_data_0_7: isi-0-data-0-7 { 19*4882a593Smuzhiyun atmel,pins = 20*4882a593Smuzhiyun <AT91_PIOC 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D0, conflicts with LCDDAT0 */ 21*4882a593Smuzhiyun AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D1, conflicts with LCDDAT1 */ 22*4882a593Smuzhiyun AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D2, conflicts with LCDDAT2 */ 23*4882a593Smuzhiyun AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D3, conflicts with LCDDAT3 */ 24*4882a593Smuzhiyun AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D4, conflicts with LCDDAT4 */ 25*4882a593Smuzhiyun AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D5, conflicts with LCDDAT5 */ 26*4882a593Smuzhiyun AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D6, conflicts with LCDDAT6 */ 27*4882a593Smuzhiyun AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D7, conflicts with LCDDAT7 */ 28*4882a593Smuzhiyun AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_PCK, conflicts with LCDDAT12 */ 29*4882a593Smuzhiyun AT91_PIOC 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_HSYNC, conflicts with LCDDAT14 */ 30*4882a593Smuzhiyun AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* ISI_VSYNC, conflicts with LCDDAT13 */ 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun pinctrl_isi_data_8_9: isi-0-data-8-9 { 34*4882a593Smuzhiyun atmel,pins = 35*4882a593Smuzhiyun <AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D8, conflicts with LCDDAT8 */ 36*4882a593Smuzhiyun AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with LCDDAT9 */ 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun pinctrl_isi_data_10_11: isi-0-data-10-11 { 40*4882a593Smuzhiyun atmel,pins = 41*4882a593Smuzhiyun <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D10, conflicts with LCDDAT10 */ 42*4882a593Smuzhiyun AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with LCDDAT11 */ 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun pmc: pmc@fffffc00 { 48*4882a593Smuzhiyun periphck { 49*4882a593Smuzhiyun isi_clk: isi_clk@25 { 50*4882a593Smuzhiyun #clock-cells = <0>; 51*4882a593Smuzhiyun reg = <25>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun isi: isi@f8048000 { 57*4882a593Smuzhiyun compatible = "atmel,at91sam9g45-isi"; 58*4882a593Smuzhiyun reg = <0xf8048000 0x4000>; 59*4882a593Smuzhiyun interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; 60*4882a593Smuzhiyun pinctrl-names = "default"; 61*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_isi_data_0_7>; 62*4882a593Smuzhiyun clocks = <&isi_clk>; 63*4882a593Smuzhiyun clock-names = "isi_clk"; 64*4882a593Smuzhiyun status = "disabled"; 65*4882a593Smuzhiyun port { 66*4882a593Smuzhiyun #address-cells = <1>; 67*4882a593Smuzhiyun #size-cells = <0>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun}; 73