1*4882a593Smuzhiyun#include <dt-bindings/clock/ast2500-scu.h> 2*4882a593Smuzhiyun#include <dt-bindings/reset/ast2500-reset.h> 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include "ast2500.dtsi" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun scu: clock-controller@1e6e2000 { 8*4882a593Smuzhiyun compatible = "aspeed,ast2500-scu"; 9*4882a593Smuzhiyun reg = <0x1e6e2000 0x1000>; 10*4882a593Smuzhiyun u-boot,dm-pre-reloc; 11*4882a593Smuzhiyun #clock-cells = <1>; 12*4882a593Smuzhiyun #reset-cells = <1>; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun rst: reset-controller { 16*4882a593Smuzhiyun u-boot,dm-pre-reloc; 17*4882a593Smuzhiyun compatible = "aspeed,ast2500-reset"; 18*4882a593Smuzhiyun aspeed,wdt = <&wdt1>; 19*4882a593Smuzhiyun #reset-cells = <1>; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun sdrammc: sdrammc@1e6e0000 { 23*4882a593Smuzhiyun u-boot,dm-pre-reloc; 24*4882a593Smuzhiyun compatible = "aspeed,ast2500-sdrammc"; 25*4882a593Smuzhiyun reg = <0x1e6e0000 0x174 26*4882a593Smuzhiyun 0x1e6e0200 0x1d4 >; 27*4882a593Smuzhiyun #reset-cells = <1>; 28*4882a593Smuzhiyun clocks = <&scu PLL_MPLL>; 29*4882a593Smuzhiyun resets = <&rst AST_RESET_SDRAM>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun ahb { 33*4882a593Smuzhiyun u-boot,dm-pre-reloc; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun apb { 36*4882a593Smuzhiyun u-boot,dm-pre-reloc; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun&uart1 { 43*4882a593Smuzhiyun clocks = <&scu PCLK_UART1>; 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun&uart2 { 47*4882a593Smuzhiyun clocks = <&scu PCLK_UART2>; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&uart3 { 51*4882a593Smuzhiyun clocks = <&scu PCLK_UART3>; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&uart4 { 55*4882a593Smuzhiyun clocks = <&scu PCLK_UART4>; 56*4882a593Smuzhiyun}; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun&uart5 { 59*4882a593Smuzhiyun clocks = <&scu PCLK_UART5>; 60*4882a593Smuzhiyun}; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun&timer { 63*4882a593Smuzhiyun u-boot,dm-pre-reloc; 64*4882a593Smuzhiyun}; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun&mac0 { 67*4882a593Smuzhiyun clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>; 68*4882a593Smuzhiyun}; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun&mac1 { 71*4882a593Smuzhiyun clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>; 72*4882a593Smuzhiyun}; 73