1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2016 Marvell Technology Group Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 5*4882a593Smuzhiyun * of the GPLv2 or the X11 license, at your option. Note that this dual 6*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 7*4882a593Smuzhiyun * whole. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * a) This library is free software; you can redistribute it and/or 10*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 11*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of the 12*4882a593Smuzhiyun * License, or (at your option) any later version. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * This library is distributed in the hope that it will be useful, 15*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*4882a593Smuzhiyun * GNU General Public License for more details. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * Or, alternatively, 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 22*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 23*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 24*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 25*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 26*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 27*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 28*4882a593Smuzhiyun * conditions: 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 31*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun/* 44*4882a593Smuzhiyun * Device Tree file for Marvell Armada CP110 Slave. 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun#include <dt-bindings/comphy/comphy_data.h> 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun/ { 50*4882a593Smuzhiyun cp110-slave { 51*4882a593Smuzhiyun #address-cells = <2>; 52*4882a593Smuzhiyun #size-cells = <2>; 53*4882a593Smuzhiyun compatible = "simple-bus"; 54*4882a593Smuzhiyun interrupt-parent = <&gic>; 55*4882a593Smuzhiyun ranges; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun config-space { 58*4882a593Smuzhiyun #address-cells = <1>; 59*4882a593Smuzhiyun #size-cells = <1>; 60*4882a593Smuzhiyun compatible = "simple-bus"; 61*4882a593Smuzhiyun interrupt-parent = <&gic>; 62*4882a593Smuzhiyun ranges = <0x0 0x0 0xf4000000 0x2000000>; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun cps_ethernet: ethernet@0 { 65*4882a593Smuzhiyun compatible = "marvell,armada-7k-pp22"; 66*4882a593Smuzhiyun reg = <0x0 0x100000>, <0x129000 0xb000>; 67*4882a593Smuzhiyun clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>; 68*4882a593Smuzhiyun clock-names = "pp_clk", "gop_clk", "mg_clk"; 69*4882a593Smuzhiyun status = "disabled"; 70*4882a593Smuzhiyun dma-coherent; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun cps_eth0: eth0 { 73*4882a593Smuzhiyun interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 74*4882a593Smuzhiyun port-id = <0>; 75*4882a593Smuzhiyun gop-port-id = <0>; 76*4882a593Smuzhiyun status = "disabled"; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun cps_eth1: eth1 { 80*4882a593Smuzhiyun interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 81*4882a593Smuzhiyun port-id = <1>; 82*4882a593Smuzhiyun gop-port-id = <2>; 83*4882a593Smuzhiyun status = "disabled"; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun cps_eth2: eth2 { 87*4882a593Smuzhiyun interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 88*4882a593Smuzhiyun port-id = <2>; 89*4882a593Smuzhiyun gop-port-id = <3>; 90*4882a593Smuzhiyun status = "disabled"; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun cps_mdio: mdio@12a200 { 95*4882a593Smuzhiyun #address-cells = <1>; 96*4882a593Smuzhiyun #size-cells = <0>; 97*4882a593Smuzhiyun compatible = "marvell,orion-mdio"; 98*4882a593Smuzhiyun reg = <0x12a200 0x10>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun cps_syscon0: system-controller@440000 { 102*4882a593Smuzhiyun compatible = "marvell,cp110-system-controller0", 103*4882a593Smuzhiyun "syscon"; 104*4882a593Smuzhiyun reg = <0x440000 0x1000>; 105*4882a593Smuzhiyun #clock-cells = <2>; 106*4882a593Smuzhiyun core-clock-output-names = 107*4882a593Smuzhiyun "cps-apll", "cps-ppv2-core", "cps-eip", 108*4882a593Smuzhiyun "cps-core", "cps-nand-core"; 109*4882a593Smuzhiyun gate-clock-output-names = 110*4882a593Smuzhiyun "cps-audio", "cps-communit", "cps-nand", 111*4882a593Smuzhiyun "cps-ppv2", "cps-sdio", "cps-mg-domain", 112*4882a593Smuzhiyun "cps-mg-core", "cps-xor1", "cps-xor0", 113*4882a593Smuzhiyun "cps-gop-dp", "none", "cps-pcie_x10", 114*4882a593Smuzhiyun "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor", 115*4882a593Smuzhiyun "cps-sata", "cps-sata-usb", "cps-main", 116*4882a593Smuzhiyun "cps-sd-mmc", "none", "none", 117*4882a593Smuzhiyun "cps-slow-io", "cps-usb3h0", "cps-usb3h1", 118*4882a593Smuzhiyun "cps-usb3dev", "cps-eip150", "cps-eip197"; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun cps_pinctl: cps-pinctl@440000 { 122*4882a593Smuzhiyun compatible = "marvell,mvebu-pinctrl", 123*4882a593Smuzhiyun "marvell,a80x0-cp1-pinctrl"; 124*4882a593Smuzhiyun bank-name ="cp1-110"; 125*4882a593Smuzhiyun reg = <0x440000 0x20>; 126*4882a593Smuzhiyun pin-count = <63>; 127*4882a593Smuzhiyun max-func = <0xf>; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 { 130*4882a593Smuzhiyun marvell,pins = < 0 1 2 3 4 5 6 7 131*4882a593Smuzhiyun 8 9 10 11 >; 132*4882a593Smuzhiyun marvell,function = <3>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun cps_spi1_pins: cps-spi-pins-1 { 135*4882a593Smuzhiyun marvell,pins = < 13 14 15 16 >; 136*4882a593Smuzhiyun marvell,function = <3>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun cps_gpio0: gpio@440100 { 141*4882a593Smuzhiyun compatible = "marvell,orion-gpio"; 142*4882a593Smuzhiyun reg = <0x440100 0x40>; 143*4882a593Smuzhiyun ngpios = <32>; 144*4882a593Smuzhiyun gpiobase = <20>; 145*4882a593Smuzhiyun gpio-controller; 146*4882a593Smuzhiyun #gpio-cells = <2>; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun cps_gpio1: gpio@440140 { 150*4882a593Smuzhiyun compatible = "marvell,orion-gpio"; 151*4882a593Smuzhiyun reg = <0x440140 0x40>; 152*4882a593Smuzhiyun ngpios = <31>; 153*4882a593Smuzhiyun gpiobase = <52>; 154*4882a593Smuzhiyun gpio-controller; 155*4882a593Smuzhiyun #gpio-cells = <2>; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun cps_sata0: sata@540000 { 159*4882a593Smuzhiyun compatible = "marvell,armada-8k-ahci"; 160*4882a593Smuzhiyun reg = <0x540000 0x30000>; 161*4882a593Smuzhiyun interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 162*4882a593Smuzhiyun clocks = <&cps_syscon0 1 15>; 163*4882a593Smuzhiyun status = "disabled"; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun cps_usb3_0: usb3@500000 { 167*4882a593Smuzhiyun compatible = "marvell,armada-8k-xhci", 168*4882a593Smuzhiyun "generic-xhci"; 169*4882a593Smuzhiyun reg = <0x500000 0x4000>; 170*4882a593Smuzhiyun dma-coherent; 171*4882a593Smuzhiyun interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 172*4882a593Smuzhiyun clocks = <&cps_syscon0 1 22>; 173*4882a593Smuzhiyun status = "disabled"; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun cps_usb3_1: usb3@510000 { 177*4882a593Smuzhiyun compatible = "marvell,armada-8k-xhci", 178*4882a593Smuzhiyun "generic-xhci"; 179*4882a593Smuzhiyun reg = <0x510000 0x4000>; 180*4882a593Smuzhiyun dma-coherent; 181*4882a593Smuzhiyun interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 182*4882a593Smuzhiyun clocks = <&cps_syscon0 1 23>; 183*4882a593Smuzhiyun status = "disabled"; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun cps_xor0: xor@6a0000 { 187*4882a593Smuzhiyun compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 188*4882a593Smuzhiyun reg = <0x6a0000 0x1000>, 189*4882a593Smuzhiyun <0x6b0000 0x1000>; 190*4882a593Smuzhiyun dma-coherent; 191*4882a593Smuzhiyun msi-parent = <&gic_v2m0>; 192*4882a593Smuzhiyun clocks = <&cps_syscon0 1 8>; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun cps_xor1: xor@6c0000 { 196*4882a593Smuzhiyun compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 197*4882a593Smuzhiyun reg = <0x6c0000 0x1000>, 198*4882a593Smuzhiyun <0x6d0000 0x1000>; 199*4882a593Smuzhiyun dma-coherent; 200*4882a593Smuzhiyun msi-parent = <&gic_v2m0>; 201*4882a593Smuzhiyun clocks = <&cps_syscon0 1 7>; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun cps_spi0: spi@700600 { 205*4882a593Smuzhiyun compatible = "marvell,armada-380-spi"; 206*4882a593Smuzhiyun reg = <0x700600 0x50>; 207*4882a593Smuzhiyun #address-cells = <0x1>; 208*4882a593Smuzhiyun #size-cells = <0x0>; 209*4882a593Smuzhiyun cell-index = <1>; 210*4882a593Smuzhiyun clocks = <&cps_syscon0 0 3>; 211*4882a593Smuzhiyun status = "disabled"; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun cps_spi1: spi@700680 { 215*4882a593Smuzhiyun compatible = "marvell,armada-380-spi"; 216*4882a593Smuzhiyun reg = <0x700680 0x50>; 217*4882a593Smuzhiyun #address-cells = <1>; 218*4882a593Smuzhiyun #size-cells = <0>; 219*4882a593Smuzhiyun cell-index = <2>; 220*4882a593Smuzhiyun clocks = <&cps_syscon0 1 21>; 221*4882a593Smuzhiyun status = "disabled"; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun cps_i2c0: i2c@701000 { 225*4882a593Smuzhiyun compatible = "marvell,mv78230-i2c"; 226*4882a593Smuzhiyun reg = <0x701000 0x20>; 227*4882a593Smuzhiyun #address-cells = <1>; 228*4882a593Smuzhiyun #size-cells = <0>; 229*4882a593Smuzhiyun interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 230*4882a593Smuzhiyun clocks = <&cps_syscon0 1 21>; 231*4882a593Smuzhiyun status = "disabled"; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun cps_i2c1: i2c@701100 { 235*4882a593Smuzhiyun compatible = "marvell,mv78230-i2c"; 236*4882a593Smuzhiyun reg = <0x701100 0x20>; 237*4882a593Smuzhiyun #address-cells = <1>; 238*4882a593Smuzhiyun #size-cells = <0>; 239*4882a593Smuzhiyun interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 240*4882a593Smuzhiyun clocks = <&cps_syscon0 1 21>; 241*4882a593Smuzhiyun status = "disabled"; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun cps_comphy: comphy@441000 { 245*4882a593Smuzhiyun compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; 246*4882a593Smuzhiyun reg = <0x441000 0x8>, 247*4882a593Smuzhiyun <0x120000 0x8>; 248*4882a593Smuzhiyun mux-bitcount = <4>; 249*4882a593Smuzhiyun max-lanes = <6>; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun cps_utmi0: utmi@580000 { 253*4882a593Smuzhiyun compatible = "marvell,mvebu-utmi-2.6.0"; 254*4882a593Smuzhiyun reg = <0x580000 0x1000>, /* utmi-unit */ 255*4882a593Smuzhiyun <0x440420 0x4>, /* usb-cfg */ 256*4882a593Smuzhiyun <0x440440 0x4>; /* utmi-cfg */ 257*4882a593Smuzhiyun utmi-port = <UTMI_PHY_TO_USB3_HOST0>; 258*4882a593Smuzhiyun status = "disabled"; 259*4882a593Smuzhiyun }; 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun cps_pcie0: pcie@f4600000 { 263*4882a593Smuzhiyun compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 264*4882a593Smuzhiyun reg = <0 0xf4600000 0 0x10000>, 265*4882a593Smuzhiyun <0 0xfaf00000 0 0x80000>; 266*4882a593Smuzhiyun reg-names = "ctrl", "config"; 267*4882a593Smuzhiyun #address-cells = <3>; 268*4882a593Smuzhiyun #size-cells = <2>; 269*4882a593Smuzhiyun #interrupt-cells = <1>; 270*4882a593Smuzhiyun device_type = "pci"; 271*4882a593Smuzhiyun dma-coherent; 272*4882a593Smuzhiyun msi-parent = <&gic_v2m0>; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun bus-range = <0 0xff>; 275*4882a593Smuzhiyun ranges = 276*4882a593Smuzhiyun /* downstream I/O */ 277*4882a593Smuzhiyun <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000 278*4882a593Smuzhiyun /* non-prefetchable memory */ 279*4882a593Smuzhiyun 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; 280*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 281*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 282*4882a593Smuzhiyun interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 283*4882a593Smuzhiyun num-lanes = <1>; 284*4882a593Smuzhiyun clocks = <&cps_syscon0 1 13>; 285*4882a593Smuzhiyun status = "disabled"; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun cps_pcie1: pcie@f4620000 { 289*4882a593Smuzhiyun compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 290*4882a593Smuzhiyun reg = <0 0xf4620000 0 0x10000>, 291*4882a593Smuzhiyun <0 0xfbf00000 0 0x80000>; 292*4882a593Smuzhiyun reg-names = "ctrl", "config"; 293*4882a593Smuzhiyun #address-cells = <3>; 294*4882a593Smuzhiyun #size-cells = <2>; 295*4882a593Smuzhiyun #interrupt-cells = <1>; 296*4882a593Smuzhiyun device_type = "pci"; 297*4882a593Smuzhiyun dma-coherent; 298*4882a593Smuzhiyun msi-parent = <&gic_v2m0>; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun bus-range = <0 0xff>; 301*4882a593Smuzhiyun ranges = 302*4882a593Smuzhiyun /* downstream I/O */ 303*4882a593Smuzhiyun <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000 304*4882a593Smuzhiyun /* non-prefetchable memory */ 305*4882a593Smuzhiyun 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; 306*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 307*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 308*4882a593Smuzhiyun interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun num-lanes = <1>; 311*4882a593Smuzhiyun clocks = <&cps_syscon0 1 11>; 312*4882a593Smuzhiyun status = "disabled"; 313*4882a593Smuzhiyun }; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun cps_pcie2: pcie@f4640000 { 316*4882a593Smuzhiyun compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 317*4882a593Smuzhiyun reg = <0 0xf4640000 0 0x10000>, 318*4882a593Smuzhiyun <0 0xfcf00000 0 0x80000>; 319*4882a593Smuzhiyun reg-names = "ctrl", "config"; 320*4882a593Smuzhiyun #address-cells = <3>; 321*4882a593Smuzhiyun #size-cells = <2>; 322*4882a593Smuzhiyun #interrupt-cells = <1>; 323*4882a593Smuzhiyun device_type = "pci"; 324*4882a593Smuzhiyun dma-coherent; 325*4882a593Smuzhiyun msi-parent = <&gic_v2m0>; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun bus-range = <0 0xff>; 328*4882a593Smuzhiyun ranges = 329*4882a593Smuzhiyun /* downstream I/O */ 330*4882a593Smuzhiyun <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000 331*4882a593Smuzhiyun /* non-prefetchable memory */ 332*4882a593Smuzhiyun 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; 333*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 334*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 335*4882a593Smuzhiyun interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun num-lanes = <1>; 338*4882a593Smuzhiyun clocks = <&cps_syscon0 1 12>; 339*4882a593Smuzhiyun status = "disabled"; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun}; 343