1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2017 Marvell Technology Group Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 5*4882a593Smuzhiyun * of the GPLv2 or the X11 license, at your option. Note that this dual 6*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 7*4882a593Smuzhiyun * whole. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * a) This library is free software; you can redistribute it and/or 10*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 11*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of the 12*4882a593Smuzhiyun * License, or (at your option) any later version. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * This library is distributed in the hope that it will be useful, 15*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*4882a593Smuzhiyun * GNU General Public License for more details. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * Or, alternatively, 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 22*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 23*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 24*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 25*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 26*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 27*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 28*4882a593Smuzhiyun * conditions: 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 31*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun/* 44*4882a593Smuzhiyun * Device Tree file for Marvell Armada 7040 Development board platform 45*4882a593Smuzhiyun * Boot device: NAND, 0xE (SW3) 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun#include "armada-7040.dtsi" 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun/ { 51*4882a593Smuzhiyun model = "Marvell Armada 7040 DB board with NAND"; 52*4882a593Smuzhiyun compatible = "marvell,armada7040-db-nand", "marvell,armada7040-db", 53*4882a593Smuzhiyun "marvell,armada7040", "marvell,armada-ap806-quad", 54*4882a593Smuzhiyun "marvell,armada-ap806"; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun chosen { 57*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun aliases { 61*4882a593Smuzhiyun i2c0 = &cpm_i2c0; 62*4882a593Smuzhiyun spi0 = &cpm_spi1; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun memory@00000000 { 66*4882a593Smuzhiyun device_type = "memory"; 67*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x80000000>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&ap_pinctl { 72*4882a593Smuzhiyun /* MPP Bus: 73*4882a593Smuzhiyun * SDIO [0-5] 74*4882a593Smuzhiyun * UART0 [11,19] 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun /* 0 1 2 3 4 5 6 7 8 9 */ 77*4882a593Smuzhiyun pin-func = < 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0 78*4882a593Smuzhiyun 0x0 0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 >; 79*4882a593Smuzhiyun}; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun&uart0 { 82*4882a593Smuzhiyun status = "okay"; 83*4882a593Smuzhiyun}; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun&cpm_pcie2 { 87*4882a593Smuzhiyun status = "okay"; 88*4882a593Smuzhiyun}; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun&cpm_i2c0 { 91*4882a593Smuzhiyun pinctrl-names = "default"; 92*4882a593Smuzhiyun pinctrl-0 = <&cpm_i2c0_pins>; 93*4882a593Smuzhiyun status = "okay"; 94*4882a593Smuzhiyun clock-frequency = <100000>; 95*4882a593Smuzhiyun}; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun&cpm_pinctl { 98*4882a593Smuzhiyun /* MPP Bus: 99*4882a593Smuzhiyun * AUDIO [0-5] 100*4882a593Smuzhiyun * GBE [6-11] 101*4882a593Smuzhiyun * SS_PWDN [12] 102*4882a593Smuzhiyun * NF_RBn [13] 103*4882a593Smuzhiyun * GPIO [14] 104*4882a593Smuzhiyun * DEV_BUS [15-27] 105*4882a593Smuzhiyun * SATA1 [28] 106*4882a593Smuzhiyun * UART0 [29-30] 107*4882a593Smuzhiyun * MSS_VTT_EN [31] 108*4882a593Smuzhiyun * SMI [32,34] 109*4882a593Smuzhiyun * XSMI [35-36] 110*4882a593Smuzhiyun * I2C [37-38] 111*4882a593Smuzhiyun * RGMII1 [44-55] 112*4882a593Smuzhiyun * SD [56-61] 113*4882a593Smuzhiyun * GPIO [62] 114*4882a593Smuzhiyun */ 115*4882a593Smuzhiyun /* 0 1 2 3 4 5 6 7 8 9 */ 116*4882a593Smuzhiyun pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3 117*4882a593Smuzhiyun 0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1 118*4882a593Smuzhiyun 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x9 0xa 119*4882a593Smuzhiyun 0xa 0x0 0x7 0x0 0x7 0x7 0x7 0x2 0x2 0x0 120*4882a593Smuzhiyun 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1 121*4882a593Smuzhiyun 0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe 122*4882a593Smuzhiyun 0xe 0xe 0x0>; 123*4882a593Smuzhiyun}; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun&cpm_spi1 { 126*4882a593Smuzhiyun pinctrl-names = "default"; 127*4882a593Smuzhiyun pinctrl-0 = <&cpm_spi0_pins>; 128*4882a593Smuzhiyun status = "disabled"; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun spi-flash@0 { 131*4882a593Smuzhiyun #address-cells = <0x1>; 132*4882a593Smuzhiyun #size-cells = <0x1>; 133*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 134*4882a593Smuzhiyun reg = <0x0>; 135*4882a593Smuzhiyun spi-max-frequency = <20000000>; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun partitions { 138*4882a593Smuzhiyun compatible = "fixed-partitions"; 139*4882a593Smuzhiyun #address-cells = <1>; 140*4882a593Smuzhiyun #size-cells = <1>; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun partition@0 { 143*4882a593Smuzhiyun label = "U-Boot"; 144*4882a593Smuzhiyun reg = <0x0 0x200000>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun partition@400000 { 148*4882a593Smuzhiyun label = "Filesystem"; 149*4882a593Smuzhiyun reg = <0x200000 0xe00000>; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun}; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun&cpm_sata0 { 156*4882a593Smuzhiyun status = "okay"; 157*4882a593Smuzhiyun}; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun&cpm_usb3_0 { 160*4882a593Smuzhiyun status = "okay"; 161*4882a593Smuzhiyun}; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun&cpm_usb3_1 { 164*4882a593Smuzhiyun status = "okay"; 165*4882a593Smuzhiyun}; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun&cpm_comphy { 168*4882a593Smuzhiyun phy0 { 169*4882a593Smuzhiyun phy-type = <PHY_TYPE_SGMII2>; 170*4882a593Smuzhiyun phy-speed = <PHY_SPEED_3_125G>; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun phy1 { 174*4882a593Smuzhiyun phy-type = <PHY_TYPE_USB3_HOST0>; 175*4882a593Smuzhiyun phy-speed = <PHY_SPEED_5G>; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun phy2 { 179*4882a593Smuzhiyun phy-type = <PHY_TYPE_SGMII0>; 180*4882a593Smuzhiyun phy-speed = <PHY_SPEED_1_25G>; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun phy3 { 184*4882a593Smuzhiyun phy-type = <PHY_TYPE_SATA1>; 185*4882a593Smuzhiyun phy-speed = <PHY_SPEED_5G>; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun phy4 { 189*4882a593Smuzhiyun phy-type = <PHY_TYPE_USB3_HOST1>; 190*4882a593Smuzhiyun phy-speed = <PHY_SPEED_5G>; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun phy5 { 194*4882a593Smuzhiyun phy-type = <PHY_TYPE_PEX2>; 195*4882a593Smuzhiyun phy-speed = <PHY_SPEED_5G>; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun}; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun&cpm_nand { 200*4882a593Smuzhiyun status = "okay"; 201*4882a593Smuzhiyun}; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun&cpm_utmi0 { 204*4882a593Smuzhiyun status = "okay"; 205*4882a593Smuzhiyun}; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun&cpm_utmi1 { 208*4882a593Smuzhiyun status = "okay"; 209*4882a593Smuzhiyun}; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun&ap_sdhci0 { 212*4882a593Smuzhiyun status = "okay"; 213*4882a593Smuzhiyun bus-width = <4>; 214*4882a593Smuzhiyun no-1-8-v; 215*4882a593Smuzhiyun non-removable; 216*4882a593Smuzhiyun}; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun&cpm_sdhci0 { 219*4882a593Smuzhiyun status = "okay"; 220*4882a593Smuzhiyun bus-width = <4>; 221*4882a593Smuzhiyun no-1-8-v; 222*4882a593Smuzhiyun non-removable; 223*4882a593Smuzhiyun}; 224