1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Device Tree file for Marvell Armada 385 development board 3*4882a593Smuzhiyun * (DB-88F6820-AMC) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Marvell 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Gregory CLEMENT <gregory.clement@free-electrons.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 10*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual 11*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 12*4882a593Smuzhiyun * whole. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * a) This file is licensed under the terms of the GNU General Public 15*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without 16*4882a593Smuzhiyun * any warranty of any kind, whether express or implied. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * Or, alternatively, 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 21*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 22*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 23*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 24*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 25*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 26*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 27*4882a593Smuzhiyun * conditions: 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 30*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 33*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 34*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 35*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 36*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 37*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 38*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 39*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun/dts-v1/; 43*4882a593Smuzhiyun#include "armada-385.dtsi" 44*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun/ { 47*4882a593Smuzhiyun model = "Marvell Armada 385 AMC"; 48*4882a593Smuzhiyun compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380"; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun chosen { 51*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun aliases { 55*4882a593Smuzhiyun ethernet0 = ð0; 56*4882a593Smuzhiyun ethernet1 = ð1; 57*4882a593Smuzhiyun i2c0 = &i2c0; 58*4882a593Smuzhiyun spi1 = &spi1; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun memory { 62*4882a593Smuzhiyun device_type = "memory"; 63*4882a593Smuzhiyun reg = <0x00000000 0x80000000>; /* 2 GB */ 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun soc { 67*4882a593Smuzhiyun ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 68*4882a593Smuzhiyun MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun internal-regs { 71*4882a593Smuzhiyun i2c@11000 { 72*4882a593Smuzhiyun clock-frequency = <100000>; 73*4882a593Smuzhiyun u-boot,i2c-slave-addr = <0x0>; 74*4882a593Smuzhiyun pinctrl-names = "default"; 75*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 76*4882a593Smuzhiyun status = "okay"; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun serial@12000 { 80*4882a593Smuzhiyun /* 81*4882a593Smuzhiyun * Exported on the micro USB connector CON16 82*4882a593Smuzhiyun * through an FTDI 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun pinctrl-names = "default"; 86*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 87*4882a593Smuzhiyun status = "okay"; 88*4882a593Smuzhiyun u-boot,dm-pre-reloc; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun ethernet@34000 { 92*4882a593Smuzhiyun status = "okay"; 93*4882a593Smuzhiyun phy = <&phy1>; 94*4882a593Smuzhiyun phy-mode = "sgmii"; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun usb@58000 { 98*4882a593Smuzhiyun status = "okay"; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun ethernet@70000 { 102*4882a593Smuzhiyun pinctrl-names = "default"; 103*4882a593Smuzhiyun /* 104*4882a593Smuzhiyun * The Reference Clock 0 is used to provide a 105*4882a593Smuzhiyun * clock to the PHY 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; 108*4882a593Smuzhiyun status = "okay"; 109*4882a593Smuzhiyun phy = <&phy0>; 110*4882a593Smuzhiyun phy-mode = "rgmii-id"; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun mdio@72004 { 115*4882a593Smuzhiyun pinctrl-names = "default"; 116*4882a593Smuzhiyun pinctrl-0 = <&mdio_pins>; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun phy0: ethernet-phy@1 { 119*4882a593Smuzhiyun reg = <1>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun phy1: ethernet-phy@0 { 123*4882a593Smuzhiyun reg = <0>; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun flash@d0000 { 128*4882a593Smuzhiyun status = "okay"; 129*4882a593Smuzhiyun num-cs = <1>; 130*4882a593Smuzhiyun marvell,nand-keep-config; 131*4882a593Smuzhiyun marvell,nand-enable-arbiter; 132*4882a593Smuzhiyun nand-on-flash-bbt; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun pcie-controller { 137*4882a593Smuzhiyun status = "okay"; 138*4882a593Smuzhiyun pcie@1,0 { 139*4882a593Smuzhiyun /* Port 0, Lane 0 */ 140*4882a593Smuzhiyun status = "okay"; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun}; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun&spi1 { 148*4882a593Smuzhiyun pinctrl-names = "default"; 149*4882a593Smuzhiyun pinctrl-0 = <&spi1_pins>; 150*4882a593Smuzhiyun status = "okay"; 151*4882a593Smuzhiyun u-boot,dm-pre-reloc; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun spi-flash@0 { 154*4882a593Smuzhiyun u-boot,dm-pre-reloc; 155*4882a593Smuzhiyun #address-cells = <1>; 156*4882a593Smuzhiyun #size-cells = <1>; 157*4882a593Smuzhiyun compatible = "st,m25p128", "jedec,spi-nor", "spi-flash"; 158*4882a593Smuzhiyun reg = <0>; /* Chip select 0 */ 159*4882a593Smuzhiyun spi-max-frequency = <50000000>; 160*4882a593Smuzhiyun m25p,fast-read; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun}; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun&refclk { 165*4882a593Smuzhiyun clock-frequency = <20000000>; 166*4882a593Smuzhiyun}; 167