1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 6*4882a593Smuzhiyun * published by the Free Software Foundation. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/* AM437x SK EVM */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/dts-v1/; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include "am4372.dtsi" 14*4882a593Smuzhiyun#include <dt-bindings/pinctrl/am43xx.h> 15*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 16*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 17*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun/ { 20*4882a593Smuzhiyun model = "TI AM437x SK EVM"; 21*4882a593Smuzhiyun compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43"; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun aliases { 24*4882a593Smuzhiyun display0 = &lcd0; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun chosen { 28*4882a593Smuzhiyun stdout-path = &uart0; 29*4882a593Smuzhiyun tick-timer = &timer2; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun backlight { 33*4882a593Smuzhiyun compatible = "pwm-backlight"; 34*4882a593Smuzhiyun pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; 35*4882a593Smuzhiyun brightness-levels = <0 51 53 56 62 75 101 152 255>; 36*4882a593Smuzhiyun default-brightness-level = <8>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun sound { 40*4882a593Smuzhiyun compatible = "ti,da830-evm-audio"; 41*4882a593Smuzhiyun ti,model = "AM437x-SK-EVM"; 42*4882a593Smuzhiyun ti,audio-codec = <&tlv320aic3106>; 43*4882a593Smuzhiyun ti,mcasp-controller = <&mcasp1>; 44*4882a593Smuzhiyun ti,codec-clock-rate = <24000000>; 45*4882a593Smuzhiyun ti,audio-routing = 46*4882a593Smuzhiyun "Headphone Jack", "HPLOUT", 47*4882a593Smuzhiyun "Headphone Jack", "HPROUT"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun matrix_keypad: matrix_keypad@0 { 51*4882a593Smuzhiyun compatible = "gpio-matrix-keypad"; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun pinctrl-names = "default"; 54*4882a593Smuzhiyun pinctrl-0 = <&matrix_keypad_pins>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun debounce-delay-ms = <5>; 57*4882a593Smuzhiyun col-scan-delay-us = <5>; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ 60*4882a593Smuzhiyun &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */ 63*4882a593Smuzhiyun &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun linux,keymap = < 66*4882a593Smuzhiyun MATRIX_KEY(0, 0, KEY_DOWN) 67*4882a593Smuzhiyun MATRIX_KEY(0, 1, KEY_RIGHT) 68*4882a593Smuzhiyun MATRIX_KEY(1, 0, KEY_LEFT) 69*4882a593Smuzhiyun MATRIX_KEY(1, 1, KEY_UP) 70*4882a593Smuzhiyun >; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun leds { 74*4882a593Smuzhiyun compatible = "gpio-leds"; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun pinctrl-names = "default"; 77*4882a593Smuzhiyun pinctrl-0 = <&leds_pins>; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun led@0 { 80*4882a593Smuzhiyun label = "am437x-sk:red:heartbeat"; 81*4882a593Smuzhiyun gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ 82*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 83*4882a593Smuzhiyun default-state = "off"; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun led@1 { 87*4882a593Smuzhiyun label = "am437x-sk:green:mmc1"; 88*4882a593Smuzhiyun gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ 89*4882a593Smuzhiyun linux,default-trigger = "mmc0"; 90*4882a593Smuzhiyun default-state = "off"; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun led@2 { 94*4882a593Smuzhiyun label = "am437x-sk:blue:cpu0"; 95*4882a593Smuzhiyun gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ 96*4882a593Smuzhiyun linux,default-trigger = "cpu0"; 97*4882a593Smuzhiyun default-state = "off"; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun led@3 { 101*4882a593Smuzhiyun label = "am437x-sk:blue:usr3"; 102*4882a593Smuzhiyun gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ 103*4882a593Smuzhiyun default-state = "off"; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun lcd0: display { 108*4882a593Smuzhiyun compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi"; 109*4882a593Smuzhiyun label = "lcd"; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun pinctrl-names = "default"; 112*4882a593Smuzhiyun pinctrl-0 = <&lcd_pins>; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun panel-timing { 117*4882a593Smuzhiyun clock-frequency = <9000000>; 118*4882a593Smuzhiyun hactive = <480>; 119*4882a593Smuzhiyun vactive = <272>; 120*4882a593Smuzhiyun hfront-porch = <2>; 121*4882a593Smuzhiyun hback-porch = <2>; 122*4882a593Smuzhiyun hsync-len = <41>; 123*4882a593Smuzhiyun vfront-porch = <2>; 124*4882a593Smuzhiyun vback-porch = <2>; 125*4882a593Smuzhiyun vsync-len = <10>; 126*4882a593Smuzhiyun hsync-active = <0>; 127*4882a593Smuzhiyun vsync-active = <0>; 128*4882a593Smuzhiyun de-active = <1>; 129*4882a593Smuzhiyun pixelclk-active = <1>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun port { 133*4882a593Smuzhiyun lcd_in: endpoint { 134*4882a593Smuzhiyun remote-endpoint = <&dpi_out>; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun}; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun&am43xx_pinmux { 141*4882a593Smuzhiyun matrix_keypad_pins: matrix_keypad_pins { 142*4882a593Smuzhiyun pinctrl-single,pins = < 143*4882a593Smuzhiyun 0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ 144*4882a593Smuzhiyun 0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ 145*4882a593Smuzhiyun 0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ 146*4882a593Smuzhiyun 0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ 147*4882a593Smuzhiyun >; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun leds_pins: leds_pins { 151*4882a593Smuzhiyun pinctrl-single,pins = < 152*4882a593Smuzhiyun 0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ 153*4882a593Smuzhiyun 0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ 154*4882a593Smuzhiyun 0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ 155*4882a593Smuzhiyun 0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ 156*4882a593Smuzhiyun >; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun i2c0_pins: i2c0_pins { 160*4882a593Smuzhiyun pinctrl-single,pins = < 161*4882a593Smuzhiyun 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 162*4882a593Smuzhiyun 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 163*4882a593Smuzhiyun >; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun i2c1_pins: i2c1_pins { 167*4882a593Smuzhiyun pinctrl-single,pins = < 168*4882a593Smuzhiyun 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ 169*4882a593Smuzhiyun 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ 170*4882a593Smuzhiyun >; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun mmc1_pins: pinmux_mmc1_pins { 174*4882a593Smuzhiyun pinctrl-single,pins = < 175*4882a593Smuzhiyun 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ 176*4882a593Smuzhiyun 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ 177*4882a593Smuzhiyun 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ 178*4882a593Smuzhiyun 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ 179*4882a593Smuzhiyun 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ 180*4882a593Smuzhiyun 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ 181*4882a593Smuzhiyun 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 182*4882a593Smuzhiyun >; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun ecap0_pins: backlight_pins { 186*4882a593Smuzhiyun pinctrl-single,pins = < 187*4882a593Smuzhiyun 0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ 188*4882a593Smuzhiyun >; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun edt_ft5306_ts_pins: edt_ft5306_ts_pins { 192*4882a593Smuzhiyun pinctrl-single,pins = < 193*4882a593Smuzhiyun 0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ 194*4882a593Smuzhiyun 0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ 195*4882a593Smuzhiyun >; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun vpfe0_pins_default: vpfe0_pins_default { 199*4882a593Smuzhiyun pinctrl-single,pins = < 200*4882a593Smuzhiyun 0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ 201*4882a593Smuzhiyun 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ 202*4882a593Smuzhiyun 0x1b8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/ 203*4882a593Smuzhiyun 0x1bc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/ 204*4882a593Smuzhiyun 0x1c0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ 205*4882a593Smuzhiyun 0x1c4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ 206*4882a593Smuzhiyun 0x1c8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ 207*4882a593Smuzhiyun 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ 208*4882a593Smuzhiyun 0x20c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ 209*4882a593Smuzhiyun 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ 210*4882a593Smuzhiyun 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ 211*4882a593Smuzhiyun 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ 212*4882a593Smuzhiyun 0x21c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ 213*4882a593Smuzhiyun 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ 214*4882a593Smuzhiyun 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ 215*4882a593Smuzhiyun >; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun vpfe0_pins_sleep: vpfe0_pins_sleep { 219*4882a593Smuzhiyun pinctrl-single,pins = < 220*4882a593Smuzhiyun 0x1b0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 221*4882a593Smuzhiyun 0x1b4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 222*4882a593Smuzhiyun 0x1b8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 223*4882a593Smuzhiyun 0x1bc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 224*4882a593Smuzhiyun 0x1c0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 225*4882a593Smuzhiyun 0x1c4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 226*4882a593Smuzhiyun 0x1c8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 227*4882a593Smuzhiyun 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 228*4882a593Smuzhiyun 0x20c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 229*4882a593Smuzhiyun 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 230*4882a593Smuzhiyun 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 231*4882a593Smuzhiyun 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 232*4882a593Smuzhiyun 0x21c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 233*4882a593Smuzhiyun 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 234*4882a593Smuzhiyun 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 235*4882a593Smuzhiyun >; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun cpsw_default: cpsw_default { 239*4882a593Smuzhiyun pinctrl-single,pins = < 240*4882a593Smuzhiyun /* Slave 1 */ 241*4882a593Smuzhiyun 0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ 242*4882a593Smuzhiyun 0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 243*4882a593Smuzhiyun 0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ 244*4882a593Smuzhiyun 0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ 245*4882a593Smuzhiyun 0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ 246*4882a593Smuzhiyun 0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ 247*4882a593Smuzhiyun 0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ 248*4882a593Smuzhiyun 0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 249*4882a593Smuzhiyun 0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ 250*4882a593Smuzhiyun 0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ 251*4882a593Smuzhiyun 0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ 252*4882a593Smuzhiyun 0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun /* Slave 2 */ 255*4882a593Smuzhiyun 0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ 256*4882a593Smuzhiyun 0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ 257*4882a593Smuzhiyun 0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ 258*4882a593Smuzhiyun 0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ 259*4882a593Smuzhiyun 0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ 260*4882a593Smuzhiyun 0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ 261*4882a593Smuzhiyun 0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ 262*4882a593Smuzhiyun 0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ 263*4882a593Smuzhiyun 0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ 264*4882a593Smuzhiyun 0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ 265*4882a593Smuzhiyun 0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ 266*4882a593Smuzhiyun 0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ 267*4882a593Smuzhiyun >; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun cpsw_sleep: cpsw_sleep { 271*4882a593Smuzhiyun pinctrl-single,pins = < 272*4882a593Smuzhiyun /* Slave 1 reset value */ 273*4882a593Smuzhiyun 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) 274*4882a593Smuzhiyun 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 275*4882a593Smuzhiyun 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 276*4882a593Smuzhiyun 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 277*4882a593Smuzhiyun 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) 278*4882a593Smuzhiyun 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) 279*4882a593Smuzhiyun 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) 280*4882a593Smuzhiyun 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) 281*4882a593Smuzhiyun 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) 282*4882a593Smuzhiyun 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 283*4882a593Smuzhiyun 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) 284*4882a593Smuzhiyun 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun /* Slave 2 reset value */ 287*4882a593Smuzhiyun 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) 288*4882a593Smuzhiyun 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) 289*4882a593Smuzhiyun 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) 290*4882a593Smuzhiyun 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) 291*4882a593Smuzhiyun 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) 292*4882a593Smuzhiyun 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) 293*4882a593Smuzhiyun 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) 294*4882a593Smuzhiyun 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) 295*4882a593Smuzhiyun 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) 296*4882a593Smuzhiyun 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) 297*4882a593Smuzhiyun 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) 298*4882a593Smuzhiyun 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) 299*4882a593Smuzhiyun >; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun davinci_mdio_default: davinci_mdio_default { 303*4882a593Smuzhiyun pinctrl-single,pins = < 304*4882a593Smuzhiyun /* MDIO */ 305*4882a593Smuzhiyun 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 306*4882a593Smuzhiyun 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ 307*4882a593Smuzhiyun >; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun davinci_mdio_sleep: davinci_mdio_sleep { 311*4882a593Smuzhiyun pinctrl-single,pins = < 312*4882a593Smuzhiyun /* MDIO reset value */ 313*4882a593Smuzhiyun 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 314*4882a593Smuzhiyun 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 315*4882a593Smuzhiyun >; 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun dss_pins: dss_pins { 319*4882a593Smuzhiyun pinctrl-single,pins = < 320*4882a593Smuzhiyun 0x020 (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ 321*4882a593Smuzhiyun 0x024 (PIN_OUTPUT | MUX_MODE1) 322*4882a593Smuzhiyun 0x028 (PIN_OUTPUT | MUX_MODE1) 323*4882a593Smuzhiyun 0x02c (PIN_OUTPUT | MUX_MODE1) 324*4882a593Smuzhiyun 0x030 (PIN_OUTPUT | MUX_MODE1) 325*4882a593Smuzhiyun 0x034 (PIN_OUTPUT | MUX_MODE1) 326*4882a593Smuzhiyun 0x038 (PIN_OUTPUT | MUX_MODE1) 327*4882a593Smuzhiyun 0x03c (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ 328*4882a593Smuzhiyun 0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ 329*4882a593Smuzhiyun 0x0a4 (PIN_OUTPUT | MUX_MODE0) 330*4882a593Smuzhiyun 0x0a8 (PIN_OUTPUT | MUX_MODE0) 331*4882a593Smuzhiyun 0x0ac (PIN_OUTPUT | MUX_MODE0) 332*4882a593Smuzhiyun 0x0b0 (PIN_OUTPUT | MUX_MODE0) 333*4882a593Smuzhiyun 0x0b4 (PIN_OUTPUT | MUX_MODE0) 334*4882a593Smuzhiyun 0x0b8 (PIN_OUTPUT | MUX_MODE0) 335*4882a593Smuzhiyun 0x0bc (PIN_OUTPUT | MUX_MODE0) 336*4882a593Smuzhiyun 0x0c0 (PIN_OUTPUT | MUX_MODE0) 337*4882a593Smuzhiyun 0x0c4 (PIN_OUTPUT | MUX_MODE0) 338*4882a593Smuzhiyun 0x0c8 (PIN_OUTPUT | MUX_MODE0) 339*4882a593Smuzhiyun 0x0cc (PIN_OUTPUT | MUX_MODE0) 340*4882a593Smuzhiyun 0x0d0 (PIN_OUTPUT | MUX_MODE0) 341*4882a593Smuzhiyun 0x0d4 (PIN_OUTPUT | MUX_MODE0) 342*4882a593Smuzhiyun 0x0d8 (PIN_OUTPUT | MUX_MODE0) 343*4882a593Smuzhiyun 0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ 344*4882a593Smuzhiyun 0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ 345*4882a593Smuzhiyun 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ 346*4882a593Smuzhiyun 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ 347*4882a593Smuzhiyun 0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun >; 350*4882a593Smuzhiyun }; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun qspi_pins: qspi_pins { 353*4882a593Smuzhiyun pinctrl-single,pins = < 354*4882a593Smuzhiyun 0x7c (PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ 355*4882a593Smuzhiyun 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ 356*4882a593Smuzhiyun 0x90 (PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ 357*4882a593Smuzhiyun 0x94 (PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ 358*4882a593Smuzhiyun 0x98 (PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */ 359*4882a593Smuzhiyun 0x9c (PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ 360*4882a593Smuzhiyun >; 361*4882a593Smuzhiyun }; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun mcasp1_pins: mcasp1_pins { 364*4882a593Smuzhiyun pinctrl-single,pins = < 365*4882a593Smuzhiyun 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ 366*4882a593Smuzhiyun 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ 367*4882a593Smuzhiyun 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ 368*4882a593Smuzhiyun 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 369*4882a593Smuzhiyun >; 370*4882a593Smuzhiyun }; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun lcd_pins: lcd_pins { 373*4882a593Smuzhiyun pinctrl-single,pins = < 374*4882a593Smuzhiyun 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ 375*4882a593Smuzhiyun >; 376*4882a593Smuzhiyun }; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun usb1_pins: usb1_pins { 379*4882a593Smuzhiyun pinctrl-single,pins = < 380*4882a593Smuzhiyun 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ 381*4882a593Smuzhiyun >; 382*4882a593Smuzhiyun }; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun usb2_pins: usb2_pins { 385*4882a593Smuzhiyun pinctrl-single,pins = < 386*4882a593Smuzhiyun 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ 387*4882a593Smuzhiyun >; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun}; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun&i2c0 { 392*4882a593Smuzhiyun status = "okay"; 393*4882a593Smuzhiyun pinctrl-names = "default"; 394*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 395*4882a593Smuzhiyun clock-frequency = <400000>; 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun tps@24 { 398*4882a593Smuzhiyun compatible = "ti,tps65218"; 399*4882a593Smuzhiyun reg = <0x24>; 400*4882a593Smuzhiyun interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 401*4882a593Smuzhiyun interrupt-controller; 402*4882a593Smuzhiyun #interrupt-cells = <2>; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun dcdc1: regulator-dcdc1 { 405*4882a593Smuzhiyun compatible = "ti,tps65218-dcdc1"; 406*4882a593Smuzhiyun /* VDD_CORE limits min of OPP50 and max of OPP100 */ 407*4882a593Smuzhiyun regulator-name = "vdd_core"; 408*4882a593Smuzhiyun regulator-min-microvolt = <912000>; 409*4882a593Smuzhiyun regulator-max-microvolt = <1144000>; 410*4882a593Smuzhiyun regulator-boot-on; 411*4882a593Smuzhiyun regulator-always-on; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun dcdc2: regulator-dcdc2 { 415*4882a593Smuzhiyun compatible = "ti,tps65218-dcdc2"; 416*4882a593Smuzhiyun /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ 417*4882a593Smuzhiyun regulator-name = "vdd_mpu"; 418*4882a593Smuzhiyun regulator-min-microvolt = <912000>; 419*4882a593Smuzhiyun regulator-max-microvolt = <1378000>; 420*4882a593Smuzhiyun regulator-boot-on; 421*4882a593Smuzhiyun regulator-always-on; 422*4882a593Smuzhiyun }; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun dcdc3: regulator-dcdc3 { 425*4882a593Smuzhiyun compatible = "ti,tps65218-dcdc3"; 426*4882a593Smuzhiyun regulator-name = "vdds_ddr"; 427*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 428*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 429*4882a593Smuzhiyun regulator-boot-on; 430*4882a593Smuzhiyun regulator-always-on; 431*4882a593Smuzhiyun }; 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun dcdc4: regulator-dcdc4 { 434*4882a593Smuzhiyun compatible = "ti,tps65218-dcdc4"; 435*4882a593Smuzhiyun regulator-name = "v3_3d"; 436*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 437*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 438*4882a593Smuzhiyun regulator-boot-on; 439*4882a593Smuzhiyun regulator-always-on; 440*4882a593Smuzhiyun }; 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun ldo1: regulator-ldo1 { 443*4882a593Smuzhiyun compatible = "ti,tps65218-ldo1"; 444*4882a593Smuzhiyun regulator-name = "v1_8d"; 445*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 446*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 447*4882a593Smuzhiyun regulator-boot-on; 448*4882a593Smuzhiyun regulator-always-on; 449*4882a593Smuzhiyun }; 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun power-button { 452*4882a593Smuzhiyun compatible = "ti,tps65218-pwrbutton"; 453*4882a593Smuzhiyun status = "okay"; 454*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_EDGE_BOTH>; 455*4882a593Smuzhiyun }; 456*4882a593Smuzhiyun }; 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun at24@50 { 459*4882a593Smuzhiyun compatible = "at24,24c256"; 460*4882a593Smuzhiyun pagesize = <64>; 461*4882a593Smuzhiyun reg = <0x50>; 462*4882a593Smuzhiyun }; 463*4882a593Smuzhiyun}; 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun&i2c1 { 466*4882a593Smuzhiyun status = "okay"; 467*4882a593Smuzhiyun pinctrl-names = "default"; 468*4882a593Smuzhiyun pinctrl-0 = <&i2c1_pins>; 469*4882a593Smuzhiyun clock-frequency = <400000>; 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun edt-ft5306@38 { 472*4882a593Smuzhiyun status = "okay"; 473*4882a593Smuzhiyun compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; 474*4882a593Smuzhiyun pinctrl-names = "default"; 475*4882a593Smuzhiyun pinctrl-0 = <&edt_ft5306_ts_pins>; 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun reg = <0x38>; 478*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 479*4882a593Smuzhiyun interrupts = <31 0>; 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun touchscreen-size-x = <480>; 484*4882a593Smuzhiyun touchscreen-size-y = <272>; 485*4882a593Smuzhiyun }; 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun tlv320aic3106: tlv320aic3106@1b { 488*4882a593Smuzhiyun compatible = "ti,tlv320aic3106"; 489*4882a593Smuzhiyun reg = <0x1b>; 490*4882a593Smuzhiyun status = "okay"; 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun /* Regulators */ 493*4882a593Smuzhiyun AVDD-supply = <&dcdc4>; 494*4882a593Smuzhiyun IOVDD-supply = <&dcdc4>; 495*4882a593Smuzhiyun DRVDD-supply = <&dcdc4>; 496*4882a593Smuzhiyun DVDD-supply = <&ldo1>; 497*4882a593Smuzhiyun }; 498*4882a593Smuzhiyun 499*4882a593Smuzhiyun lis331dlh@18 { 500*4882a593Smuzhiyun compatible = "st,lis331dlh"; 501*4882a593Smuzhiyun reg = <0x18>; 502*4882a593Smuzhiyun status = "okay"; 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun Vdd-supply = <&dcdc4>; 505*4882a593Smuzhiyun Vdd_IO-supply = <&dcdc4>; 506*4882a593Smuzhiyun interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>; 507*4882a593Smuzhiyun }; 508*4882a593Smuzhiyun}; 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun&epwmss0 { 511*4882a593Smuzhiyun status = "okay"; 512*4882a593Smuzhiyun}; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun&ecap0 { 515*4882a593Smuzhiyun status = "okay"; 516*4882a593Smuzhiyun pinctrl-names = "default"; 517*4882a593Smuzhiyun pinctrl-0 = <&ecap0_pins>; 518*4882a593Smuzhiyun}; 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun&gpio0 { 521*4882a593Smuzhiyun status = "okay"; 522*4882a593Smuzhiyun}; 523*4882a593Smuzhiyun 524*4882a593Smuzhiyun&gpio1 { 525*4882a593Smuzhiyun status = "okay"; 526*4882a593Smuzhiyun}; 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun&gpio5 { 529*4882a593Smuzhiyun status = "okay"; 530*4882a593Smuzhiyun}; 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun&mmc1 { 533*4882a593Smuzhiyun status = "okay"; 534*4882a593Smuzhiyun pinctrl-names = "default"; 535*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun vmmc-supply = <&dcdc4>; 538*4882a593Smuzhiyun bus-width = <4>; 539*4882a593Smuzhiyun cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 540*4882a593Smuzhiyun}; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun&usb2_phy1 { 543*4882a593Smuzhiyun status = "okay"; 544*4882a593Smuzhiyun}; 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun&usb1 { 547*4882a593Smuzhiyun dr_mode = "peripheral"; 548*4882a593Smuzhiyun status = "okay"; 549*4882a593Smuzhiyun pinctrl-names = "default"; 550*4882a593Smuzhiyun pinctrl-0 = <&usb1_pins>; 551*4882a593Smuzhiyun}; 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun&usb2_phy2 { 554*4882a593Smuzhiyun status = "okay"; 555*4882a593Smuzhiyun}; 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun&usb2 { 558*4882a593Smuzhiyun dr_mode = "host"; 559*4882a593Smuzhiyun status = "okay"; 560*4882a593Smuzhiyun pinctrl-names = "default"; 561*4882a593Smuzhiyun pinctrl-0 = <&usb2_pins>; 562*4882a593Smuzhiyun}; 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun&qspi { 565*4882a593Smuzhiyun status = "okay"; 566*4882a593Smuzhiyun pinctrl-names = "default"; 567*4882a593Smuzhiyun pinctrl-0 = <&qspi_pins>; 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun spi-max-frequency = <48000000>; 570*4882a593Smuzhiyun m25p80@0 { 571*4882a593Smuzhiyun compatible = "mx66l51235l","spi-flash"; 572*4882a593Smuzhiyun spi-max-frequency = <48000000>; 573*4882a593Smuzhiyun reg = <0>; 574*4882a593Smuzhiyun spi-cpol; 575*4882a593Smuzhiyun spi-cpha; 576*4882a593Smuzhiyun spi-tx-bus-width = <1>; 577*4882a593Smuzhiyun spi-rx-bus-width = <4>; 578*4882a593Smuzhiyun #address-cells = <1>; 579*4882a593Smuzhiyun #size-cells = <1>; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun /* MTD partition table. 582*4882a593Smuzhiyun * The ROM checks the first 512KiB 583*4882a593Smuzhiyun * for a valid file to boot(XIP). 584*4882a593Smuzhiyun */ 585*4882a593Smuzhiyun partition@0 { 586*4882a593Smuzhiyun label = "QSPI.U_BOOT"; 587*4882a593Smuzhiyun reg = <0x00000000 0x000080000>; 588*4882a593Smuzhiyun }; 589*4882a593Smuzhiyun partition@1 { 590*4882a593Smuzhiyun label = "QSPI.U_BOOT.backup"; 591*4882a593Smuzhiyun reg = <0x00080000 0x00080000>; 592*4882a593Smuzhiyun }; 593*4882a593Smuzhiyun partition@2 { 594*4882a593Smuzhiyun label = "QSPI.U-BOOT-SPL_OS"; 595*4882a593Smuzhiyun reg = <0x00100000 0x00010000>; 596*4882a593Smuzhiyun }; 597*4882a593Smuzhiyun partition@3 { 598*4882a593Smuzhiyun label = "QSPI.U_BOOT_ENV"; 599*4882a593Smuzhiyun reg = <0x00110000 0x00010000>; 600*4882a593Smuzhiyun }; 601*4882a593Smuzhiyun partition@4 { 602*4882a593Smuzhiyun label = "QSPI.U-BOOT-ENV.backup"; 603*4882a593Smuzhiyun reg = <0x00120000 0x00010000>; 604*4882a593Smuzhiyun }; 605*4882a593Smuzhiyun partition@5 { 606*4882a593Smuzhiyun label = "QSPI.KERNEL"; 607*4882a593Smuzhiyun reg = <0x00130000 0x0800000>; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun partition@6 { 610*4882a593Smuzhiyun label = "QSPI.FILESYSTEM"; 611*4882a593Smuzhiyun reg = <0x00930000 0x36D0000>; 612*4882a593Smuzhiyun }; 613*4882a593Smuzhiyun }; 614*4882a593Smuzhiyun}; 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun&mac { 617*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 618*4882a593Smuzhiyun pinctrl-0 = <&cpsw_default>; 619*4882a593Smuzhiyun pinctrl-1 = <&cpsw_sleep>; 620*4882a593Smuzhiyun dual_emac = <1>; 621*4882a593Smuzhiyun status = "okay"; 622*4882a593Smuzhiyun}; 623*4882a593Smuzhiyun 624*4882a593Smuzhiyun&davinci_mdio { 625*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 626*4882a593Smuzhiyun pinctrl-0 = <&davinci_mdio_default>; 627*4882a593Smuzhiyun pinctrl-1 = <&davinci_mdio_sleep>; 628*4882a593Smuzhiyun status = "okay"; 629*4882a593Smuzhiyun}; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun&cpsw_emac0 { 632*4882a593Smuzhiyun phy_id = <&davinci_mdio>, <4>; 633*4882a593Smuzhiyun phy-mode = "rgmii"; 634*4882a593Smuzhiyun dual_emac_res_vlan = <1>; 635*4882a593Smuzhiyun}; 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun&cpsw_emac1 { 638*4882a593Smuzhiyun phy_id = <&davinci_mdio>, <5>; 639*4882a593Smuzhiyun phy-mode = "rgmii"; 640*4882a593Smuzhiyun dual_emac_res_vlan = <2>; 641*4882a593Smuzhiyun}; 642*4882a593Smuzhiyun 643*4882a593Smuzhiyun&elm { 644*4882a593Smuzhiyun status = "okay"; 645*4882a593Smuzhiyun}; 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun&mcasp1 { 648*4882a593Smuzhiyun pinctrl-names = "default"; 649*4882a593Smuzhiyun pinctrl-0 = <&mcasp1_pins>; 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun status = "okay"; 652*4882a593Smuzhiyun 653*4882a593Smuzhiyun op-mode = <0>; 654*4882a593Smuzhiyun tdm-slots = <2>; 655*4882a593Smuzhiyun serial-dir = < 656*4882a593Smuzhiyun 0 0 1 2 657*4882a593Smuzhiyun >; 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun tx-num-evt = <1>; 660*4882a593Smuzhiyun rx-num-evt = <1>; 661*4882a593Smuzhiyun}; 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun&dss { 664*4882a593Smuzhiyun status = "okay"; 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun pinctrl-names = "default"; 667*4882a593Smuzhiyun pinctrl-0 = <&dss_pins>; 668*4882a593Smuzhiyun 669*4882a593Smuzhiyun port { 670*4882a593Smuzhiyun dpi_out: endpoint@0 { 671*4882a593Smuzhiyun remote-endpoint = <&lcd_in>; 672*4882a593Smuzhiyun data-lines = <24>; 673*4882a593Smuzhiyun }; 674*4882a593Smuzhiyun }; 675*4882a593Smuzhiyun}; 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun&rtc { 678*4882a593Smuzhiyun status = "okay"; 679*4882a593Smuzhiyun}; 680*4882a593Smuzhiyun 681*4882a593Smuzhiyun&wdt { 682*4882a593Smuzhiyun status = "okay"; 683*4882a593Smuzhiyun}; 684*4882a593Smuzhiyun 685*4882a593Smuzhiyun&cpu { 686*4882a593Smuzhiyun cpu0-supply = <&dcdc2>; 687*4882a593Smuzhiyun}; 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun&vpfe0 { 690*4882a593Smuzhiyun status = "okay"; 691*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 692*4882a593Smuzhiyun pinctrl-0 = <&vpfe0_pins_default>; 693*4882a593Smuzhiyun pinctrl-1 = <&vpfe0_pins_sleep>; 694*4882a593Smuzhiyun 695*4882a593Smuzhiyun /* Camera port */ 696*4882a593Smuzhiyun port { 697*4882a593Smuzhiyun vpfe0_ep: endpoint { 698*4882a593Smuzhiyun /* remote-endpoint = <&sensor>; add once we have it */ 699*4882a593Smuzhiyun ti,am437x-vpfe-interface = <0>; 700*4882a593Smuzhiyun bus-width = <8>; 701*4882a593Smuzhiyun hsync-active = <0>; 702*4882a593Smuzhiyun vsync-active = <0>; 703*4882a593Smuzhiyun }; 704*4882a593Smuzhiyun }; 705*4882a593Smuzhiyun}; 706