xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/am335x-rut.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (C) 2014 DENX Software Engineering GmbH
3*4882a593Smuzhiyun * Heiko Schocher <hs@denx.de>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Based on:
6*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
9*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as
10*4882a593Smuzhiyun * published by the Free Software Foundation.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun/dts-v1/;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun#include "am33xx.dtsi"
15*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun/ {
18*4882a593Smuzhiyun	model = "RUT";
19*4882a593Smuzhiyun	compatible = "ti,am335x-evm", "ti,am33xx";
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	buzzer {
22*4882a593Smuzhiyun		compatible = "pwm-beeper";
23*4882a593Smuzhiyun		pwms = <&ecap0 0 16000 0>;
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	chosen {
27*4882a593Smuzhiyun		stdout-path = &uart0;
28*4882a593Smuzhiyun		tick-timer = &timer2;
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	cpus {
32*4882a593Smuzhiyun		cpu@0 {
33*4882a593Smuzhiyun			cpu0-supply = <&dcdc2_reg>;
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	gpio_keys: powerfail-keys {
38*4882a593Smuzhiyun		compatible = "gpio-keys";
39*4882a593Smuzhiyun		#address-cells = <1>;
40*4882a593Smuzhiyun		#size-cells = <0>;
41*4882a593Smuzhiyun		autorepeat;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		pwr-fail0 {
44*4882a593Smuzhiyun			label = "power-fail";
45*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
46*4882a593Smuzhiyun			gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
47*4882a593Smuzhiyun			gpio-key,wakeup;
48*4882a593Smuzhiyun		};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun		pwr-fail1 {
51*4882a593Smuzhiyun			label = "power-fail-redundant";
52*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
53*4882a593Smuzhiyun			gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
54*4882a593Smuzhiyun			gpio-key,wakeup;
55*4882a593Smuzhiyun		};
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	leds {
59*4882a593Smuzhiyun		compatible = "gpio-leds";
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun		led_green {
62*4882a593Smuzhiyun			label = "rut:green:debug:run_mode";
63*4882a593Smuzhiyun			gpios = <&gpio3 20 1>;
64*4882a593Smuzhiyun			/* activelow = 1, default trigger heartbeat */
65*4882a593Smuzhiyun		};
66*4882a593Smuzhiyun		led_yellow {
67*4882a593Smuzhiyun			label = "rut:debug:yellow:osc_ch1";
68*4882a593Smuzhiyun			gpios = <&gpio0 17 1>;
69*4882a593Smuzhiyun			/* activelow = 1, default trigger mmc0 */
70*4882a593Smuzhiyun		};
71*4882a593Smuzhiyun		led_red {
72*4882a593Smuzhiyun			label = "rut:debug:red:osc_ch2";
73*4882a593Smuzhiyun			gpios = <&gpio0 16 1>;
74*4882a593Smuzhiyun			/* activelow = 1, default trigger debug_osc_ch2 */
75*4882a593Smuzhiyun		};
76*4882a593Smuzhiyun		/* optional */
77*4882a593Smuzhiyun		led_alive {
78*4882a593Smuzhiyun			label = "rut:alive";
79*4882a593Smuzhiyun			gpios = <&gpio0 15 1>;
80*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
81*4882a593Smuzhiyun			/* activelow = 1, default trigger heartbeat */
82*4882a593Smuzhiyun		};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun	};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun	memory {
87*4882a593Smuzhiyun		device_type = "memory";
88*4882a593Smuzhiyun		reg = <0x80000000 0x10000000>; /* 256 MB */
89*4882a593Smuzhiyun	};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun	panel {
92*4882a593Smuzhiyun		compatible = "ti,tilcdc,panel";
93*4882a593Smuzhiyun		pinctrl-names = "default";
94*4882a593Smuzhiyun		pinctrl-0 = <&lcd_pins_s0>;
95*4882a593Smuzhiyun		status = "okay";
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun		/* FORMIKE_KWH043ST20_F01 */
98*4882a593Smuzhiyun		panel-info {
99*4882a593Smuzhiyun			ac-bias           = <255>;
100*4882a593Smuzhiyun			ac-bias-intrpt    = <0>;
101*4882a593Smuzhiyun			dma-burst-sz      = <16>;
102*4882a593Smuzhiyun			bpp               = <16>;
103*4882a593Smuzhiyun			fdd               = <0x80>;
104*4882a593Smuzhiyun			sync-edge         = <0>;
105*4882a593Smuzhiyun			sync-ctrl         = <1>;
106*4882a593Smuzhiyun			raster-order      = <0>;
107*4882a593Smuzhiyun			fifo-th           = <0>;
108*4882a593Smuzhiyun			tft-alt-mode      = <0>;
109*4882a593Smuzhiyun			invert-pxl-clk    = <1>;
110*4882a593Smuzhiyun		};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun		display-timings {
113*4882a593Smuzhiyun			native-mode = <&timing1>;
114*4882a593Smuzhiyun			timing1: 480x800p60 {
115*4882a593Smuzhiyun				clock-frequency = <29925000>;
116*4882a593Smuzhiyun				hactive = <480>;
117*4882a593Smuzhiyun				vactive = <800>;
118*4882a593Smuzhiyun				hfront-porch = <50>;
119*4882a593Smuzhiyun				hback-porch = <50>;
120*4882a593Smuzhiyun				hsync-len = <50>;
121*4882a593Smuzhiyun				vback-porch = <50>;
122*4882a593Smuzhiyun				vfront-porch = <50>;
123*4882a593Smuzhiyun				vsync-len = <50>;
124*4882a593Smuzhiyun				hsync-active = <1>;
125*4882a593Smuzhiyun				vsync-active = <1>;
126*4882a593Smuzhiyun			};
127*4882a593Smuzhiyun		};
128*4882a593Smuzhiyun	};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun	vmmc: fixedregulator3 {
131*4882a593Smuzhiyun		compatible = "regulator-fixed";
132*4882a593Smuzhiyun		regulator-name = "vmmc";
133*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
134*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
135*4882a593Smuzhiyun	};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun	watchdog {
138*4882a593Smuzhiyun		compatible = "linux,wdt-gpio";
139*4882a593Smuzhiyun		gpios = <&gpio0 14 0>;
140*4882a593Smuzhiyun		hw_algo = "level";
141*4882a593Smuzhiyun		hw_margin_ms = <30000>;
142*4882a593Smuzhiyun	};
143*4882a593Smuzhiyun};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun&aes {
146*4882a593Smuzhiyun	status = "okay";
147*4882a593Smuzhiyun};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun&cppi41dma  {
150*4882a593Smuzhiyun	status = "okay";
151*4882a593Smuzhiyun};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun&cpsw_emac0 {
154*4882a593Smuzhiyun	phy_id = <&davinci_mdio>, <1>;
155*4882a593Smuzhiyun	phy-mode = "rmii";
156*4882a593Smuzhiyun};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun&cpsw_emac1 {
159*4882a593Smuzhiyun	phy_id = <&davinci_mdio>, <0>;
160*4882a593Smuzhiyun	phy-mode = "rmii";
161*4882a593Smuzhiyun};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun&davinci_mdio {
164*4882a593Smuzhiyun	pinctrl-names = "default", "sleep";
165*4882a593Smuzhiyun	pinctrl-0 = <&davinci_mdio_default>;
166*4882a593Smuzhiyun	pinctrl-1 = <&davinci_mdio_sleep>;
167*4882a593Smuzhiyun	status = "okay";
168*4882a593Smuzhiyun	gpios = <&gpio2 18 0>;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun        ethernet_phy: ethernet-phy@1 {
171*4882a593Smuzhiyun                compatible = "ethernet-phy-id2000.5ce1";
172*4882a593Smuzhiyun                reg = <1>;
173*4882a593Smuzhiyun		natsemi,master_mode_fixup;
174*4882a593Smuzhiyun        };
175*4882a593Smuzhiyun};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun&elm {
178*4882a593Smuzhiyun	status = "okay";
179*4882a593Smuzhiyun};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun&epwmss0 {
182*4882a593Smuzhiyun	status = "okay";
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun	ecap0: ecap@48300100 {
185*4882a593Smuzhiyun		status = "okay";
186*4882a593Smuzhiyun		pinctrl-names = "default";
187*4882a593Smuzhiyun		pinctrl-0 = <&ecap0_pins>;
188*4882a593Smuzhiyun	};
189*4882a593Smuzhiyun};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun&epwmss1 {
192*4882a593Smuzhiyun	status = "okay";
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun	ehrpwm1: ehrpwm@48302200 {
195*4882a593Smuzhiyun		status = "okay";
196*4882a593Smuzhiyun		pinctrl-names = "default";
197*4882a593Smuzhiyun		pinctrl-0 = <&epwmss1_pins>;
198*4882a593Smuzhiyun	};
199*4882a593Smuzhiyun};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun&gpmc {
202*4882a593Smuzhiyun	pinctrl-names = "default";
203*4882a593Smuzhiyun	pinctrl-0 = <&nandflash_pins>;
204*4882a593Smuzhiyun	status = "okay";
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun	nand@0,0 {
209*4882a593Smuzhiyun		reg = <0 0 0>; /* CS0, offset 0 */
210*4882a593Smuzhiyun		nand-bus-width = <8>;
211*4882a593Smuzhiyun		ti,nand-ecc-opt = "bch8";
212*4882a593Smuzhiyun		gpmc,device-nand = "true";
213*4882a593Smuzhiyun		gpmc,device-width = <1>;
214*4882a593Smuzhiyun		gpmc,sync-clk-ps = <0>;
215*4882a593Smuzhiyun		gpmc,cs-on-ns = <0>;
216*4882a593Smuzhiyun		gpmc,cs-rd-off-ns = <57>;
217*4882a593Smuzhiyun		gpmc,cs-wr-off-ns = <57>;
218*4882a593Smuzhiyun		gpmc,adv-on-ns = <0>;
219*4882a593Smuzhiyun		gpmc,adv-rd-off-ns = <57>;
220*4882a593Smuzhiyun		gpmc,adv-wr-off-ns = <57>;
221*4882a593Smuzhiyun		gpmc,we-on-ns = <0>;
222*4882a593Smuzhiyun		gpmc,we-off-ns = <48>;
223*4882a593Smuzhiyun		gpmc,oe-on-ns = <0>;
224*4882a593Smuzhiyun		gpmc,oe-off-ns = <57>;
225*4882a593Smuzhiyun		gpmc,access-ns = <38>;
226*4882a593Smuzhiyun		gpmc,rd-cycle-ns = <67>;
227*4882a593Smuzhiyun		gpmc,wr-cycle-ns = <67>;
228*4882a593Smuzhiyun		gpmc,wait-on-read = "true";
229*4882a593Smuzhiyun		gpmc,wait-on-write = "true";
230*4882a593Smuzhiyun		gpmc,bus-turnaround-ns = <0>;
231*4882a593Smuzhiyun		gpmc,cycle2cycle-delay-ns = <0>;
232*4882a593Smuzhiyun		gpmc,clk-activation-ns = <0>;
233*4882a593Smuzhiyun		gpmc,wait-monitoring-ns = <0>;
234*4882a593Smuzhiyun		gpmc,wr-access-ns = <96>;
235*4882a593Smuzhiyun		gpmc,wr-data-mux-bus-ns = <0>;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun		#address-cells = <1>;
238*4882a593Smuzhiyun		#size-cells = <1>;
239*4882a593Smuzhiyun		elm_id = <&elm>;
240*4882a593Smuzhiyun	};
241*4882a593Smuzhiyun};
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun&i2c0 {
244*4882a593Smuzhiyun	pinctrl-names = "default";
245*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins>;
246*4882a593Smuzhiyun	clock-frequency = <400000>;
247*4882a593Smuzhiyun	status = "okay";
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun	eeprom: eeprom@50 {
250*4882a593Smuzhiyun		compatible = "atmel,24c128";
251*4882a593Smuzhiyun		reg = <0x50>;
252*4882a593Smuzhiyun		pagesize = <32>;
253*4882a593Smuzhiyun	};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun	tps: tps@24 {
256*4882a593Smuzhiyun		reg = <0x24>;
257*4882a593Smuzhiyun	};
258*4882a593Smuzhiyun};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun&i2c1 {
261*4882a593Smuzhiyun	pinctrl-names = "default";
262*4882a593Smuzhiyun	pinctrl-0 = <&i2c1_pins>;
263*4882a593Smuzhiyun	clock-frequency = <100000>;
264*4882a593Smuzhiyun	status = "okay";
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun	atmel: atmel_mxt_ts@4a {
267*4882a593Smuzhiyun		compatible = "atmel,maxtouch";
268*4882a593Smuzhiyun		reg = <0x4a>;
269*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
270*4882a593Smuzhiyun		interrupts = <28 8>;
271*4882a593Smuzhiyun		gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
272*4882a593Smuzhiyun	};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun	temp@48 {
275*4882a593Smuzhiyun		compatible = "st,ds75";
276*4882a593Smuzhiyun		reg = <0x4c>;
277*4882a593Smuzhiyun	};
278*4882a593Smuzhiyun};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun&lcdc {
281*4882a593Smuzhiyun	status = "okay";
282*4882a593Smuzhiyun};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun&mac {
285*4882a593Smuzhiyun	pinctrl-names = "default", "sleep";
286*4882a593Smuzhiyun	pinctrl-0 = <&cpsw_default>;
287*4882a593Smuzhiyun	pinctrl-1 = <&cpsw_sleep>;
288*4882a593Smuzhiyun	status = "okay";
289*4882a593Smuzhiyun};
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun&mmc1 {
292*4882a593Smuzhiyun	vmmc-supply = <&vmmc>;
293*4882a593Smuzhiyun	pinctrl-names = "default";
294*4882a593Smuzhiyun	pinctrl-0 = <&mmc1_pins>;
295*4882a593Smuzhiyun	status = "okay";
296*4882a593Smuzhiyun};
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun&phy_sel {
299*4882a593Smuzhiyun	rmii-clock-ext;
300*4882a593Smuzhiyun};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun&sham {
303*4882a593Smuzhiyun	status = "okay";
304*4882a593Smuzhiyun};
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun&spi0 {
307*4882a593Smuzhiyun	pinctrl-names = "default";
308*4882a593Smuzhiyun	pinctrl-0 = <&spi0_pins>;
309*4882a593Smuzhiyun	status = "okay";
310*4882a593Smuzhiyun	spi-flash@0 {
311*4882a593Smuzhiyun		#address-cells = <1>;
312*4882a593Smuzhiyun		#size-cells = <1>;
313*4882a593Smuzhiyun		compatible = "mx25l25635e";
314*4882a593Smuzhiyun		reg = <0>; /* Chip select 0 */
315*4882a593Smuzhiyun		spi-max-frequency = <24000000>;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun		partition@0 {
318*4882a593Smuzhiyun			label = "dummy";
319*4882a593Smuzhiyun			reg = <0x0000000 0x8000>;
320*4882a593Smuzhiyun		};
321*4882a593Smuzhiyun	};
322*4882a593Smuzhiyun};
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun&spi1 {
325*4882a593Smuzhiyun	pinctrl-names = "default";
326*4882a593Smuzhiyun	pinctrl-0 = <&spi1_pins>;
327*4882a593Smuzhiyun	status = "okay";
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun	lcd_init: lcd@0 {
330*4882a593Smuzhiyun		compatible = "formike,kwh043st20";
331*4882a593Smuzhiyun		reg = <0>;
332*4882a593Smuzhiyun		reset-gpios = <&gpio3 19 0>;
333*4882a593Smuzhiyun		spi-max-frequency = <1200000>;
334*4882a593Smuzhiyun		spi-cpol;
335*4882a593Smuzhiyun		spi-cpha;
336*4882a593Smuzhiyun		power-on-delay = <10>;
337*4882a593Smuzhiyun		reset-delay = <10>;
338*4882a593Smuzhiyun	};
339*4882a593Smuzhiyun};
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun/include/ "tps65217.dtsi"
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun&tps {
344*4882a593Smuzhiyun	backlight0: backlight {
345*4882a593Smuzhiyun		isel = <1>;  /* 1 - ISET1, 2 ISET2 */
346*4882a593Smuzhiyun		fdim = <1000>; /* TPS65217_BL_FDIM_100HZ */
347*4882a593Smuzhiyun		default-brightness = <80>;
348*4882a593Smuzhiyun	};
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun	regulators {
351*4882a593Smuzhiyun		dcdc1_reg: regulator@0 {
352*4882a593Smuzhiyun			regulator-always-on;
353*4882a593Smuzhiyun		};
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun		dcdc2_reg: regulator@1 {
356*4882a593Smuzhiyun			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
357*4882a593Smuzhiyun			regulator-name = "vdd_mpu";
358*4882a593Smuzhiyun			regulator-min-microvolt = <925000>;
359*4882a593Smuzhiyun			regulator-max-microvolt = <1325000>;
360*4882a593Smuzhiyun			regulator-boot-on;
361*4882a593Smuzhiyun			regulator-always-on;
362*4882a593Smuzhiyun		};
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun		dcdc3_reg: regulator@2 {
365*4882a593Smuzhiyun			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
366*4882a593Smuzhiyun			regulator-name = "vdd_core";
367*4882a593Smuzhiyun			regulator-min-microvolt = <925000>;
368*4882a593Smuzhiyun			regulator-max-microvolt = <1150000>;
369*4882a593Smuzhiyun			regulator-boot-on;
370*4882a593Smuzhiyun			regulator-always-on;
371*4882a593Smuzhiyun		};
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun		ldo1_reg: regulator@3 {
374*4882a593Smuzhiyun			regulator-always-on;
375*4882a593Smuzhiyun		};
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun		ldo2_reg: regulator@4 {
378*4882a593Smuzhiyun			regulator-always-on;
379*4882a593Smuzhiyun		};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun		ldo3_reg: regulator@5 {
382*4882a593Smuzhiyun			regulator-always-on;
383*4882a593Smuzhiyun		};
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun		ldo4_reg: regulator@6 {
386*4882a593Smuzhiyun			regulator-always-on;
387*4882a593Smuzhiyun		};
388*4882a593Smuzhiyun	};
389*4882a593Smuzhiyun};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun&tscadc {
392*4882a593Smuzhiyun	status = "okay";
393*4882a593Smuzhiyun	adc {
394*4882a593Smuzhiyun		ti,adc-channels = <4 5 6 7>;
395*4882a593Smuzhiyun	};
396*4882a593Smuzhiyun};
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun&uart0 {
399*4882a593Smuzhiyun	pinctrl-names = "default";
400*4882a593Smuzhiyun	pinctrl-0 = <&uart0_pins>;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun	status = "okay";
403*4882a593Smuzhiyun};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun&usb {
406*4882a593Smuzhiyun	status = "okay";
407*4882a593Smuzhiyun};
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun&usb_ctrl_mod {
410*4882a593Smuzhiyun	status = "okay";
411*4882a593Smuzhiyun};
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun&usb0 {
414*4882a593Smuzhiyun	dr_mode = "device";
415*4882a593Smuzhiyun	status = "okay";
416*4882a593Smuzhiyun};
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun&usb0_phy {
419*4882a593Smuzhiyun	status = "okay";
420*4882a593Smuzhiyun};
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun&am33xx_pinmux {
423*4882a593Smuzhiyun	pinctrl-names = "default";
424*4882a593Smuzhiyun	pinctrl-0 = <&clkout2_pin &gpio_pin>;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun	clkout2_pin: pinmux_clkout2_pin {
427*4882a593Smuzhiyun		pinctrl-single,pins = <
428*4882a593Smuzhiyun			0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* xdma_event_intr1.clkout2 */
429*4882a593Smuzhiyun		>;
430*4882a593Smuzhiyun	};
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun	cpsw_default: cpsw_default {
433*4882a593Smuzhiyun		pinctrl-single,pins = <
434*4882a593Smuzhiyun			/* Slave 1 */
435*4882a593Smuzhiyun			0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
436*4882a593Smuzhiyun			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.mii1_rxerr */
437*4882a593Smuzhiyun			0x114 (MUX_MODE1)	/* mii1_txen.mii1_txen */
438*4882a593Smuzhiyun			0x124 (MUX_MODE1)	/* mii1_txd1.mii1_txd1 */
439*4882a593Smuzhiyun			0x128 (MUX_MODE1)	/* mii1_txd0.mii1_txd0 */
440*4882a593Smuzhiyun			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd1.mii1_rxd1 */
441*4882a593Smuzhiyun			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd0.mii1_rxd0 */
442*4882a593Smuzhiyun			0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
443*4882a593Smuzhiyun		>;
444*4882a593Smuzhiyun	};
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun	cpsw_sleep: cpsw_sleep {
447*4882a593Smuzhiyun		pinctrl-single,pins = <
448*4882a593Smuzhiyun			/* Slave 1 reset value */
449*4882a593Smuzhiyun			0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
450*4882a593Smuzhiyun			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
451*4882a593Smuzhiyun			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
452*4882a593Smuzhiyun			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
453*4882a593Smuzhiyun			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
454*4882a593Smuzhiyun			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
455*4882a593Smuzhiyun			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
456*4882a593Smuzhiyun			0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
457*4882a593Smuzhiyun		>;
458*4882a593Smuzhiyun	};
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun	davinci_mdio_default: davinci_mdio_default {
461*4882a593Smuzhiyun		pinctrl-single,pins = <
462*4882a593Smuzhiyun			/* MDIO */
463*4882a593Smuzhiyun			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
464*4882a593Smuzhiyun			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
465*4882a593Smuzhiyun		>;
466*4882a593Smuzhiyun	};
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun	davinci_mdio_sleep: davinci_mdio_sleep {
469*4882a593Smuzhiyun		pinctrl-single,pins = <
470*4882a593Smuzhiyun			/* MDIO reset value */
471*4882a593Smuzhiyun			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
472*4882a593Smuzhiyun			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
473*4882a593Smuzhiyun		>;
474*4882a593Smuzhiyun	};
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun	ecap0_pins: ecap_pins {
477*4882a593Smuzhiyun		pinctrl-single,pins = <
478*4882a593Smuzhiyun			0x164 (MUX_MODE0)	/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 buzzer frequency: ecap.0 */
479*4882a593Smuzhiyun		>;
480*4882a593Smuzhiyun	};
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun	epwmss1_pins: epwmss_pins {
483*4882a593Smuzhiyun		pinctrl-single,pins = <
484*4882a593Smuzhiyun			0x48 (PIN_INPUT | MUX_MODE7)	/* gpmc_a2.gpio1_18 buzzer frequency: ehrpwm1A high-Z due to connected to ecap0 by R0469 */
485*4882a593Smuzhiyun			0x4c (MUX_MODE6)	/* gpmc_a3.ehrpwm1B buzzer volume pwm */
486*4882a593Smuzhiyun		>;
487*4882a593Smuzhiyun	};
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun	gpio_pin: gpio_pin {
490*4882a593Smuzhiyun		pinctrl-single,pins = <
491*4882a593Smuzhiyun			0x6c (PIN_INPUT | MUX_MODE7)		/* gpmc_a11.gpio1_27 PWR_FAIL_GPIO_SPARE */
492*4882a593Smuzhiyun			0x78 (PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7)	/* gpmc_be1n.gpio1_28 TOUCH_CHANGE_N */
493*4882a593Smuzhiyun			0x88 (PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7)		/* gpmc_csn3.gpio2_0 RUT_GPIO0_GPIO */
494*4882a593Smuzhiyun			0x118 (PIN_INPUT | MUX_MODE7)		/* gmii1_rxdv.gpio3_4 PWR_FAIL_GPIO */
495*4882a593Smuzhiyun			0x11c (MUX_MODE7)			/* mii1_txd3.gpio0_16 DEBUG_OSC_CH2_GPIO */
496*4882a593Smuzhiyun			0x120 (MUX_MODE7)			/* mii1_txd2.gpio0_17 DEBUG_OSC_CH1_GPIO */
497*4882a593Smuzhiyun			0x134 (MUX_MODE7)			/* gmii1_rxd3.gpio2_18 PHY_RSTn_GPIO */
498*4882a593Smuzhiyun			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gmii1_rxd2.gpio2_19 PHY_INT_GPIO */
499*4882a593Smuzhiyun			0x180 (MUX_MODE7)			/* uart1_rxd.gpio0_14 WATCHDOG_TRIGGER_GPIO */
500*4882a593Smuzhiyun			0x184 (MUX_MODE7)			/* uart1_txd.gpio0_15 ALIVE_LED_N_GPIO */
501*4882a593Smuzhiyun			0x1a0 (MUX_MODE7)			/* mcasp0_aclkr.gpio3_18 MAXTOUCH_RESET_GPIO */
502*4882a593Smuzhiyun			0x1a4 (MUX_MODE7)			/* mcasp0_fsr.gpio3_19 DISPLAY_RESET_GPIO */
503*4882a593Smuzhiyun			0x1a8 (MUX_MODE7)			/* mcasp0_axr1.gpio3_20 DEBUG_RUN_MODE_GPIO */
504*4882a593Smuzhiyun			0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* mcasp0_ahclkx.gpio3_21 NORFLASH_WP_GPIO */
505*4882a593Smuzhiyun			0x1b0 (PIN_OUTPUT | MUX_MODE3)		/* xdma_event_intr0.clkout1 */
506*4882a593Smuzhiyun		>;
507*4882a593Smuzhiyun	};
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun	i2c0_pins: pinmux_i2c0_pins {
510*4882a593Smuzhiyun		pinctrl-single,pins = <
511*4882a593Smuzhiyun			0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
512*4882a593Smuzhiyun			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
513*4882a593Smuzhiyun		>;
514*4882a593Smuzhiyun	};
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun	i2c1_pins: pinmux_i2c1_pins {
517*4882a593Smuzhiyun		pinctrl-single,pins = <
518*4882a593Smuzhiyun			0x168 (PIN_INPUT | MUX_MODE3)	/* uart0_ctsn.i2c1_sda */
519*4882a593Smuzhiyun			0x16c (PIN_INPUT | MUX_MODE3)	/* uart0.rtsn.i2c1_scl */
520*4882a593Smuzhiyun		>;
521*4882a593Smuzhiyun	};
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun	lcd_pins_s0: lcd_pins_s0 {
524*4882a593Smuzhiyun		pinctrl-single,pins = <
525*4882a593Smuzhiyun			0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad8.lcd_data23 */
526*4882a593Smuzhiyun			0x24 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad9.lcd_data22 */
527*4882a593Smuzhiyun			0x28 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad10.lcd_data21 */
528*4882a593Smuzhiyun			0x2c (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad11.lcd_data20 */
529*4882a593Smuzhiyun			0x30 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad12.lcd_data19 */
530*4882a593Smuzhiyun			0x34 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad13.lcd_data18 */
531*4882a593Smuzhiyun			0x38 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad14.lcd_data17 */
532*4882a593Smuzhiyun			0x3c (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad15.lcd_data16 */
533*4882a593Smuzhiyun			0xa0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data0.lcd_data0 */
534*4882a593Smuzhiyun			0xa4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data1.lcd_data1 */
535*4882a593Smuzhiyun			0xa8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data2.lcd_data2 */
536*4882a593Smuzhiyun			0xac (PIN_OUTPUT | MUX_MODE0)		/* lcd_data3.lcd_data3 */
537*4882a593Smuzhiyun			0xb0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data4.lcd_data4 */
538*4882a593Smuzhiyun			0xb4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data5.lcd_data5 */
539*4882a593Smuzhiyun			0xb8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data6.lcd_data6 */
540*4882a593Smuzhiyun			0xbc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data7.lcd_data7 */
541*4882a593Smuzhiyun			0xc0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data8.lcd_data8 */
542*4882a593Smuzhiyun			0xc4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data9.lcd_data9 */
543*4882a593Smuzhiyun			0xc8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data10.lcd_data10 */
544*4882a593Smuzhiyun			0xcc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data11.lcd_data11 */
545*4882a593Smuzhiyun			0xd0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data12.lcd_data12 */
546*4882a593Smuzhiyun			0xd4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data13.lcd_data13 */
547*4882a593Smuzhiyun			0xd8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data14.lcd_data14 */
548*4882a593Smuzhiyun			0xdc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data15.lcd_data15 */
549*4882a593Smuzhiyun			0xe0 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* lcd_vsync.lcd_vsync */
550*4882a593Smuzhiyun			0xe4 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* lcd_hsync.lcd_hsync */
551*4882a593Smuzhiyun			0xe8 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* lcd_pclk.lcd_pclk */
552*4882a593Smuzhiyun			0xec (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* lcd_ac_bias_en.lcd_ac_bias_en */
553*4882a593Smuzhiyun		>;
554*4882a593Smuzhiyun	};
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun	mmc1_pins: mmc1_pins {
557*4882a593Smuzhiyun		pinctrl-single,pins = <
558*4882a593Smuzhiyun			0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat0.mmc0_dat0 */
559*4882a593Smuzhiyun			0xf4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat1.mmc0_dat1 */
560*4882a593Smuzhiyun			0xf8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat2.mmc0_dat2 */
561*4882a593Smuzhiyun			0xfc (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat3.mmc0_dat3 */
562*4882a593Smuzhiyun			0x100 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_clk.mmc0_clk */
563*4882a593Smuzhiyun			0x104 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_cmd.mmc0_cmd */
564*4882a593Smuzhiyun		>;
565*4882a593Smuzhiyun	};
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun	nandflash_pins: pinmux_nandflash_pins {
568*4882a593Smuzhiyun		pinctrl-single,pins = <
569*4882a593Smuzhiyun			0x0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
570*4882a593Smuzhiyun			0x4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
571*4882a593Smuzhiyun			0x8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
572*4882a593Smuzhiyun			0xc (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
573*4882a593Smuzhiyun			0x10 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
574*4882a593Smuzhiyun			0x14 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
575*4882a593Smuzhiyun			0x18 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
576*4882a593Smuzhiyun			0x1c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
577*4882a593Smuzhiyun			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
578*4882a593Smuzhiyun			0x74 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
579*4882a593Smuzhiyun			0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0 */
580*4882a593Smuzhiyun			0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
581*4882a593Smuzhiyun			0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
582*4882a593Smuzhiyun			0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
583*4882a593Smuzhiyun			0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
584*4882a593Smuzhiyun		>;
585*4882a593Smuzhiyun	};
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun	spi0_pins: pinmux_spi0_pins {
588*4882a593Smuzhiyun		pinctrl-single,pins = <
589*4882a593Smuzhiyun			0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_sclk.spi0_sclk */
590*4882a593Smuzhiyun			0x154 (PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_d0.spi0_d0 */
591*4882a593Smuzhiyun			0x158 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_d1.spi0_d1 */
592*4882a593Smuzhiyun			0x15c (PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_CS0.spi0_CS0 */
593*4882a593Smuzhiyun		>;
594*4882a593Smuzhiyun	};
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun	spi1_pins: pinmux_spi1_pins {
597*4882a593Smuzhiyun		pinctrl-single,pins = <
598*4882a593Smuzhiyun			0x190 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcasp0_aclkx.spi1_sclk */
599*4882a593Smuzhiyun			0x194 (PIN_INPUT_PULLUP | MUX_MODE3)	/* mcasp0_fsx.spi1_d0 */
600*4882a593Smuzhiyun			0x198 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcasp0_axr0.spi1_d1 */
601*4882a593Smuzhiyun			0x19c (PIN_INPUT_PULLUP | MUX_MODE3)	/* mcasp0_ahclkr.spi1_cs0 */
602*4882a593Smuzhiyun		>;
603*4882a593Smuzhiyun	};
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun	uart0_pins: pinmux_uart0_pins {
606*4882a593Smuzhiyun		pinctrl-single,pins = <
607*4882a593Smuzhiyun			0x170 (PIN_INPUT | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
608*4882a593Smuzhiyun			0x174 (PIN_OUTPUT | MUX_MODE0)	/* uart0_txd.uart0_txd */
609*4882a593Smuzhiyun		>;
610*4882a593Smuzhiyun	};
611*4882a593Smuzhiyun};
612