1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2014 DENX Software Engineering GmbH 3*4882a593Smuzhiyun * Heiko Schocher <hs@denx.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Based on: 6*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 9*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 10*4882a593Smuzhiyun * published by the Free Software Foundation. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include "am33xx.dtsi" 14*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/ { 17*4882a593Smuzhiyun chosen { 18*4882a593Smuzhiyun stdout-path = &uart0; 19*4882a593Smuzhiyun tick-timer = &timer2; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun cpus { 23*4882a593Smuzhiyun cpu@0 { 24*4882a593Smuzhiyun cpu0-supply = <&vdd1_reg>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun backlight0: backlight { 29*4882a593Smuzhiyun compatible = "pwm-backlight"; 30*4882a593Smuzhiyun pwms = <&ecap0 0 50000 0>; 31*4882a593Smuzhiyun brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35 32*4882a593Smuzhiyun 38 40 43 45 48 51 53 56 58 61 63 66 68 71 33*4882a593Smuzhiyun 73 76 79 81 84 86 89 91 94 96 99 102 104 34*4882a593Smuzhiyun 107 109 112 114 117 119 122 124 127 130 35*4882a593Smuzhiyun 132 135 137 140 142 145 147 150 153 155 36*4882a593Smuzhiyun 158 160 163 165 168 170 173 175 178 181 37*4882a593Smuzhiyun 183 186 188 191 193 196 198 201 204 206 38*4882a593Smuzhiyun 209 211 214 216 219 221 224 226 229 232 39*4882a593Smuzhiyun 234 237 239 242 244 247 249 252 255>; 40*4882a593Smuzhiyun default-brightness-level = <80>; 41*4882a593Smuzhiyun power-supply = <&backlight_reg>; 42*4882a593Smuzhiyun enable-gpios = <&gpio3 16 0>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun backlight_reg: fixedregulator0 { 46*4882a593Smuzhiyun compatible = "regulator-fixed"; 47*4882a593Smuzhiyun regulator-name = "backlight_reg"; 48*4882a593Smuzhiyun regulator-boot-on; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun gpio_keys: restart-keys { 52*4882a593Smuzhiyun compatible = "gpio-keys"; 53*4882a593Smuzhiyun #address-cells = <1>; 54*4882a593Smuzhiyun #size-cells = <0>; 55*4882a593Smuzhiyun autorepeat; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun restart0 { 58*4882a593Smuzhiyun label = "restart"; 59*4882a593Smuzhiyun linux,code = <KEY_RESTART>; 60*4882a593Smuzhiyun gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; 61*4882a593Smuzhiyun gpio-key,wakeup; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun leds { 66*4882a593Smuzhiyun compatible = "gpio-leds"; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun led_blue { 69*4882a593Smuzhiyun label = "blue"; 70*4882a593Smuzhiyun gpios = <&gpio3 20 0>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun led_green { 73*4882a593Smuzhiyun label = "green"; 74*4882a593Smuzhiyun gpios = <&gpio1 31 0>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun led_red { 77*4882a593Smuzhiyun label = "red"; 78*4882a593Smuzhiyun gpios = <&gpio3 21 0>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun memory { 83*4882a593Smuzhiyun device_type = "memory"; 84*4882a593Smuzhiyun reg = <0x80000000 0x10000000>; /* 256 MB */ 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun reg_lcd_3v3: fixedregulator1 { 88*4882a593Smuzhiyun compatible = "regulator-gpio"; 89*4882a593Smuzhiyun regulator-name = "lcd-3v3"; 90*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 91*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 92*4882a593Smuzhiyun regulator-type = "voltage"; 93*4882a593Smuzhiyun startup-delay-us = <100>; 94*4882a593Smuzhiyun states = <1800000 0x1 95*4882a593Smuzhiyun 2900000 0x0>; 96*4882a593Smuzhiyun enable-at-boot; 97*4882a593Smuzhiyun gpios = <&gpio3 19 0>; 98*4882a593Smuzhiyun enable-active-high; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun vbat: fixedregulator2 { 102*4882a593Smuzhiyun compatible = "regulator-fixed"; 103*4882a593Smuzhiyun regulator-name = "vbat"; 104*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 105*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 106*4882a593Smuzhiyun regulator-boot-on; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun vmmc: fixedregulator3 { 110*4882a593Smuzhiyun compatible = "regulator-fixed"; 111*4882a593Smuzhiyun regulator-name = "vmmc"; 112*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 113*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun}; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun&cppi41dma { 118*4882a593Smuzhiyun status = "okay"; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&cpsw_emac0 { 122*4882a593Smuzhiyun phy_id = <&davinci_mdio>, <0>; 123*4882a593Smuzhiyun phy-mode = "rgmii-txid"; 124*4882a593Smuzhiyun}; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun&cpsw_emac1 { 127*4882a593Smuzhiyun phy_id = <&davinci_mdio>, <1>; 128*4882a593Smuzhiyun phy-mode = "rgmii-txid"; 129*4882a593Smuzhiyun}; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun&davinci_mdio { 132*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 133*4882a593Smuzhiyun pinctrl-0 = <&davinci_mdio_default>; 134*4882a593Smuzhiyun pinctrl-1 = <&davinci_mdio_sleep>; 135*4882a593Smuzhiyun status = "okay"; 136*4882a593Smuzhiyun}; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun&elm { 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&epwmss0 { 143*4882a593Smuzhiyun status = "okay"; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun ecap0: ecap@48300100 { 146*4882a593Smuzhiyun status = "okay"; 147*4882a593Smuzhiyun pinctrl-names = "default"; 148*4882a593Smuzhiyun pinctrl-0 = <&ecap0_pins>; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun}; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun&gpmc { 153*4882a593Smuzhiyun pinctrl-names = "default"; 154*4882a593Smuzhiyun pinctrl-0 = <&nandflash_pins>; 155*4882a593Smuzhiyun status = "okay"; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun nand@0,0 { 160*4882a593Smuzhiyun reg = <0 0 0>; /* CS0, offset 0 */ 161*4882a593Smuzhiyun nand-bus-width = <8>; 162*4882a593Smuzhiyun ti,nand-ecc-opt = "bch8"; 163*4882a593Smuzhiyun gpmc,device-nand = "true"; 164*4882a593Smuzhiyun gpmc,device-width = <1>; 165*4882a593Smuzhiyun gpmc,sync-clk-ps = <0>; 166*4882a593Smuzhiyun gpmc,cs-on-ns = <0>; 167*4882a593Smuzhiyun gpmc,cs-rd-off-ns = <44>; 168*4882a593Smuzhiyun gpmc,cs-wr-off-ns = <44>; 169*4882a593Smuzhiyun gpmc,adv-on-ns = <6>; 170*4882a593Smuzhiyun gpmc,adv-rd-off-ns = <34>; 171*4882a593Smuzhiyun gpmc,adv-wr-off-ns = <44>; 172*4882a593Smuzhiyun gpmc,we-on-ns = <0>; 173*4882a593Smuzhiyun gpmc,we-off-ns = <40>; 174*4882a593Smuzhiyun gpmc,oe-on-ns = <0>; 175*4882a593Smuzhiyun gpmc,oe-off-ns = <54>; 176*4882a593Smuzhiyun gpmc,access-ns = <64>; 177*4882a593Smuzhiyun gpmc,rd-cycle-ns = <82>; 178*4882a593Smuzhiyun gpmc,wr-cycle-ns = <82>; 179*4882a593Smuzhiyun gpmc,wait-on-read = "true"; 180*4882a593Smuzhiyun gpmc,wait-on-write = "true"; 181*4882a593Smuzhiyun gpmc,bus-turnaround-ns = <0>; 182*4882a593Smuzhiyun gpmc,cycle2cycle-delay-ns = <0>; 183*4882a593Smuzhiyun gpmc,clk-activation-ns = <0>; 184*4882a593Smuzhiyun gpmc,wait-monitoring-ns = <0>; 185*4882a593Smuzhiyun gpmc,wr-access-ns = <40>; 186*4882a593Smuzhiyun gpmc,wr-data-mux-bus-ns = <0>; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun #address-cells = <1>; 189*4882a593Smuzhiyun #size-cells = <1>; 190*4882a593Smuzhiyun elm_id = <&elm>; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun}; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun&i2c0 { 195*4882a593Smuzhiyun pinctrl-names = "default"; 196*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 197*4882a593Smuzhiyun clock-frequency = <400000>; 198*4882a593Smuzhiyun status = "okay"; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun tps: tps@2d { 201*4882a593Smuzhiyun reg = <0x2d>; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun eeprom: eeprom@50 { 204*4882a593Smuzhiyun compatible = "atmel,24c128"; 205*4882a593Smuzhiyun reg = <0x50>; 206*4882a593Smuzhiyun pagesize = <32>; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun}; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun&i2c1 { 211*4882a593Smuzhiyun pinctrl-names = "default"; 212*4882a593Smuzhiyun pinctrl-0 = <&i2c1_pins>; 213*4882a593Smuzhiyun clock-frequency = <100000>; 214*4882a593Smuzhiyun status = "okay"; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun tsl2563: tsl2563@49 { 217*4882a593Smuzhiyun compatible = "amstaos,tsl2563"; 218*4882a593Smuzhiyun reg = <0x49>; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun}; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun&i2c2 { 223*4882a593Smuzhiyun pinctrl-names = "default"; 224*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins>; 225*4882a593Smuzhiyun clock-frequency = <100000>; 226*4882a593Smuzhiyun status = "okay"; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun egalax_ts@04 { 229*4882a593Smuzhiyun compatible = "eeti,egalax_ts"; 230*4882a593Smuzhiyun reg = <0x04>; 231*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 232*4882a593Smuzhiyun interrupts = <24 2>; 233*4882a593Smuzhiyun wakeup-gpios = <&gpio1 25 0>; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun}; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun&lcdc { 238*4882a593Smuzhiyun status = "okay"; 239*4882a593Smuzhiyun}; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun&mac { 242*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 243*4882a593Smuzhiyun pinctrl-0 = <&cpsw_default>; 244*4882a593Smuzhiyun pinctrl-1 = <&cpsw_sleep>; 245*4882a593Smuzhiyun status = "okay"; 246*4882a593Smuzhiyun}; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun&mmc1 { 249*4882a593Smuzhiyun vmmc-supply = <&vmmc>; 250*4882a593Smuzhiyun bus-width = <4>; 251*4882a593Smuzhiyun cd-gpios = <&gpio0 6 0>; 252*4882a593Smuzhiyun wp-gpios = <&gpio3 18 0>; 253*4882a593Smuzhiyun status = "okay"; 254*4882a593Smuzhiyun}; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun&phy_sel { 257*4882a593Smuzhiyun rgmii-no-delay; 258*4882a593Smuzhiyun}; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun#include "tps65910.dtsi" 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun&tps { 263*4882a593Smuzhiyun vcc1-supply = <&vbat>; 264*4882a593Smuzhiyun vcc2-supply = <&vbat>; 265*4882a593Smuzhiyun vcc3-supply = <&vbat>; 266*4882a593Smuzhiyun vcc4-supply = <&vbat>; 267*4882a593Smuzhiyun vcc5-supply = <&vbat>; 268*4882a593Smuzhiyun vcc6-supply = <&vbat>; 269*4882a593Smuzhiyun vcc7-supply = <&vbat>; 270*4882a593Smuzhiyun vccio-supply = <&vbat>; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun regulators { 273*4882a593Smuzhiyun vrtc_reg: regulator@0 { 274*4882a593Smuzhiyun regulator-always-on; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun vio_reg: regulator@1 { 278*4882a593Smuzhiyun regulator-always-on; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun vdd1_reg: regulator@2 { 282*4882a593Smuzhiyun /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 283*4882a593Smuzhiyun regulator-name = "vdd_mpu"; 284*4882a593Smuzhiyun regulator-min-microvolt = <912500>; 285*4882a593Smuzhiyun regulator-max-microvolt = <1312500>; 286*4882a593Smuzhiyun regulator-boot-on; 287*4882a593Smuzhiyun regulator-always-on; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun vdd2_reg: regulator@3 { 291*4882a593Smuzhiyun /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 292*4882a593Smuzhiyun regulator-name = "vdd_core"; 293*4882a593Smuzhiyun regulator-min-microvolt = <912500>; 294*4882a593Smuzhiyun regulator-max-microvolt = <1150000>; 295*4882a593Smuzhiyun regulator-boot-on; 296*4882a593Smuzhiyun regulator-always-on; 297*4882a593Smuzhiyun }; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun vdd3_reg: regulator@4 { 300*4882a593Smuzhiyun regulator-always-on; 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun vdig1_reg: regulator@5 { 304*4882a593Smuzhiyun regulator-always-on; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun vdig2_reg: regulator@6 { 308*4882a593Smuzhiyun regulator-always-on; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun vpll_reg: regulator@7 { 312*4882a593Smuzhiyun regulator-always-on; 313*4882a593Smuzhiyun }; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun vdac_reg: regulator@8 { 316*4882a593Smuzhiyun regulator-always-on; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun vaux1_reg: regulator@9 { 320*4882a593Smuzhiyun regulator-always-on; 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun vaux2_reg: regulator@10 { 324*4882a593Smuzhiyun regulator-always-on; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun vaux33_reg: regulator@11 { 328*4882a593Smuzhiyun regulator-always-on; 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun vmmc_reg: regulator@12 { 332*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 333*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 334*4882a593Smuzhiyun regulator-always-on; 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun }; 337*4882a593Smuzhiyun}; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun&uart0 { 340*4882a593Smuzhiyun pinctrl-names = "default"; 341*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun status = "okay"; 344*4882a593Smuzhiyun}; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun&usb { 347*4882a593Smuzhiyun status = "okay"; 348*4882a593Smuzhiyun}; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun&usb_ctrl_mod { 351*4882a593Smuzhiyun status = "okay"; 352*4882a593Smuzhiyun}; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun&usb0 { 355*4882a593Smuzhiyun status = "okay"; 356*4882a593Smuzhiyun}; 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun&usb1 { 359*4882a593Smuzhiyun dr_mode = "host"; 360*4882a593Smuzhiyun status = "okay"; 361*4882a593Smuzhiyun}; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun&usb0_phy { 364*4882a593Smuzhiyun status = "okay"; 365*4882a593Smuzhiyun}; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun&usb1_phy { 368*4882a593Smuzhiyun status = "okay"; 369*4882a593Smuzhiyun}; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun&am33xx_pinmux { 372*4882a593Smuzhiyun pinctrl-names = "default"; 373*4882a593Smuzhiyun pinctrl-0 = <&clkout2_pin &gpio_pin>; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun clkout2_pin: pinmux_clkout2_pin { 376*4882a593Smuzhiyun pinctrl-single,pins = < 377*4882a593Smuzhiyun 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ 378*4882a593Smuzhiyun >; 379*4882a593Smuzhiyun }; 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun cpsw_default: cpsw_default { 382*4882a593Smuzhiyun pinctrl-single,pins = < 383*4882a593Smuzhiyun /* Slave 1 */ 384*4882a593Smuzhiyun 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 385*4882a593Smuzhiyun 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 386*4882a593Smuzhiyun 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ 387*4882a593Smuzhiyun 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ 388*4882a593Smuzhiyun 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ 389*4882a593Smuzhiyun 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ 390*4882a593Smuzhiyun 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ 391*4882a593Smuzhiyun 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ 392*4882a593Smuzhiyun 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ 393*4882a593Smuzhiyun 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ 394*4882a593Smuzhiyun 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ 395*4882a593Smuzhiyun 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ 396*4882a593Smuzhiyun >; 397*4882a593Smuzhiyun }; 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun cpsw_sleep: cpsw_sleep { 400*4882a593Smuzhiyun pinctrl-single,pins = < 401*4882a593Smuzhiyun /* Slave 1 reset value */ 402*4882a593Smuzhiyun 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 403*4882a593Smuzhiyun 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) 404*4882a593Smuzhiyun 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) 405*4882a593Smuzhiyun 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) 406*4882a593Smuzhiyun 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 407*4882a593Smuzhiyun 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 408*4882a593Smuzhiyun 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) 409*4882a593Smuzhiyun 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) 410*4882a593Smuzhiyun 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) 411*4882a593Smuzhiyun 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) 412*4882a593Smuzhiyun 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 413*4882a593Smuzhiyun 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) 414*4882a593Smuzhiyun >; 415*4882a593Smuzhiyun }; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun davinci_mdio_default: davinci_mdio_default { 418*4882a593Smuzhiyun pinctrl-single,pins = < 419*4882a593Smuzhiyun /* MDIO */ 420*4882a593Smuzhiyun 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 421*4882a593Smuzhiyun 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 422*4882a593Smuzhiyun >; 423*4882a593Smuzhiyun }; 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun davinci_mdio_sleep: davinci_mdio_sleep { 426*4882a593Smuzhiyun pinctrl-single,pins = < 427*4882a593Smuzhiyun /* MDIO reset value */ 428*4882a593Smuzhiyun 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 429*4882a593Smuzhiyun 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 430*4882a593Smuzhiyun >; 431*4882a593Smuzhiyun }; 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun ecap0_pins: ecap_pins { 434*4882a593Smuzhiyun pinctrl-single,pins = < 435*4882a593Smuzhiyun 0x198 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_axr0.gpio3_16 Backlight enable */ 436*4882a593Smuzhiyun 0x164 (MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 437*4882a593Smuzhiyun >; 438*4882a593Smuzhiyun }; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun gpio_pin: gpio_pin { 442*4882a593Smuzhiyun pinctrl-single,pins = < 443*4882a593Smuzhiyun 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 touch reset */ 444*4882a593Smuzhiyun 0x60 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 touch irq */ 445*4882a593Smuzhiyun 0x64 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a9.gpio1_25 touch power */ 446*4882a593Smuzhiyun 0x6c (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 pad14 to DFU */ 447*4882a593Smuzhiyun 0x21c (MUX_MODE0) /* usb0_drvvbus */ 448*4882a593Smuzhiyun 0x234 (MUX_MODE0) /* usb1_drvvbus */ 449*4882a593Smuzhiyun 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ 450*4882a593Smuzhiyun 0x160 (PIN_INPUT_PULLUP | MUX_MODE5) /* spi0_cs1.mmc0_sdcd */ 451*4882a593Smuzhiyun >; 452*4882a593Smuzhiyun }; 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun i2c0_pins: pinmux_i2c0_pins { 455*4882a593Smuzhiyun pinctrl-single,pins = < 456*4882a593Smuzhiyun 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 457*4882a593Smuzhiyun 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 458*4882a593Smuzhiyun >; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun i2c1_pins: pinmux_i2c1_pins { 462*4882a593Smuzhiyun pinctrl-single,pins = < 463*4882a593Smuzhiyun 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ 464*4882a593Smuzhiyun 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ 465*4882a593Smuzhiyun >; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun i2c2_pins: pinmux_i2c2_pins { 469*4882a593Smuzhiyun pinctrl-single,pins = < 470*4882a593Smuzhiyun 0x150 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_sclk.i2c2_sda */ 471*4882a593Smuzhiyun 0x154 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c2_scl */ 472*4882a593Smuzhiyun >; 473*4882a593Smuzhiyun }; 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun lcd_pins_s0: lcd_pins_s0 { 476*4882a593Smuzhiyun pinctrl-single,pins = < 477*4882a593Smuzhiyun 0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ 478*4882a593Smuzhiyun 0x24 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ 479*4882a593Smuzhiyun 0x28 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ 480*4882a593Smuzhiyun 0x2c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ 481*4882a593Smuzhiyun 0x30 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ 482*4882a593Smuzhiyun 0x34 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ 483*4882a593Smuzhiyun 0x38 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ 484*4882a593Smuzhiyun 0x3c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ 485*4882a593Smuzhiyun 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ 486*4882a593Smuzhiyun 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ 487*4882a593Smuzhiyun 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ 488*4882a593Smuzhiyun 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ 489*4882a593Smuzhiyun 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ 490*4882a593Smuzhiyun 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ 491*4882a593Smuzhiyun 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ 492*4882a593Smuzhiyun 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ 493*4882a593Smuzhiyun 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ 494*4882a593Smuzhiyun 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ 495*4882a593Smuzhiyun 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ 496*4882a593Smuzhiyun 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ 497*4882a593Smuzhiyun 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ 498*4882a593Smuzhiyun 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ 499*4882a593Smuzhiyun 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ 500*4882a593Smuzhiyun 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ 501*4882a593Smuzhiyun 0xe0 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ 502*4882a593Smuzhiyun 0xe4 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ 503*4882a593Smuzhiyun 0xe8 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ 504*4882a593Smuzhiyun 0xec (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ 505*4882a593Smuzhiyun 0x194 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_fsx.gpio3_15 LCD enable */ 506*4882a593Smuzhiyun >; 507*4882a593Smuzhiyun }; 508*4882a593Smuzhiyun 509*4882a593Smuzhiyun nandflash_pins: pinmux_nandflash_pins { 510*4882a593Smuzhiyun pinctrl-single,pins = < 511*4882a593Smuzhiyun 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 512*4882a593Smuzhiyun 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 513*4882a593Smuzhiyun 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 514*4882a593Smuzhiyun 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 515*4882a593Smuzhiyun 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 516*4882a593Smuzhiyun 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 517*4882a593Smuzhiyun 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 518*4882a593Smuzhiyun 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 519*4882a593Smuzhiyun 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 520*4882a593Smuzhiyun 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ 521*4882a593Smuzhiyun 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 522*4882a593Smuzhiyun 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 523*4882a593Smuzhiyun 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 524*4882a593Smuzhiyun 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 525*4882a593Smuzhiyun 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 526*4882a593Smuzhiyun >; 527*4882a593Smuzhiyun }; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun uart0_pins: pinmux_uart0_pins { 530*4882a593Smuzhiyun pinctrl-single,pins = < 531*4882a593Smuzhiyun 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 532*4882a593Smuzhiyun 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ 533*4882a593Smuzhiyun >; 534*4882a593Smuzhiyun }; 535*4882a593Smuzhiyun}; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun&wdt2 { 538*4882a593Smuzhiyun wdt-keep-enabled; 539*4882a593Smuzhiyun}; 540