1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 6*4882a593Smuzhiyun * published by the Free Software Foundation. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "am33xx.dtsi" 11*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "TI AM335x EVM"; 15*4882a593Smuzhiyun compatible = "ti,am335x-evm", "ti,am33xx"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun chosen { 18*4882a593Smuzhiyun stdout-path = &uart0; 19*4882a593Smuzhiyun tick-timer = &timer2; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun cpus { 23*4882a593Smuzhiyun cpu@0 { 24*4882a593Smuzhiyun cpu0-supply = <&vdd1_reg>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun memory { 29*4882a593Smuzhiyun device_type = "memory"; 30*4882a593Smuzhiyun reg = <0x80000000 0x10000000>; /* 256 MB */ 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun vbat: fixedregulator@0 { 34*4882a593Smuzhiyun compatible = "regulator-fixed"; 35*4882a593Smuzhiyun regulator-name = "vbat"; 36*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 37*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 38*4882a593Smuzhiyun regulator-boot-on; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun lis3_reg: fixedregulator@1 { 42*4882a593Smuzhiyun compatible = "regulator-fixed"; 43*4882a593Smuzhiyun regulator-name = "lis3_reg"; 44*4882a593Smuzhiyun regulator-boot-on; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun wlan_en_reg: fixedregulator@2 { 48*4882a593Smuzhiyun compatible = "regulator-fixed"; 49*4882a593Smuzhiyun regulator-name = "wlan-en-regulator"; 50*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 51*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* WLAN_EN GPIO for this board - Bank1, pin16 */ 54*4882a593Smuzhiyun gpio = <&gpio1 16 0>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* WLAN card specific delay */ 57*4882a593Smuzhiyun startup-delay-us = <70000>; 58*4882a593Smuzhiyun enable-active-high; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun matrix_keypad: matrix_keypad@0 { 62*4882a593Smuzhiyun compatible = "gpio-matrix-keypad"; 63*4882a593Smuzhiyun debounce-delay-ms = <5>; 64*4882a593Smuzhiyun col-scan-delay-us = <2>; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ 67*4882a593Smuzhiyun &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ 68*4882a593Smuzhiyun &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ 71*4882a593Smuzhiyun &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun linux,keymap = <0x0000008b /* MENU */ 74*4882a593Smuzhiyun 0x0100009e /* BACK */ 75*4882a593Smuzhiyun 0x02000069 /* LEFT */ 76*4882a593Smuzhiyun 0x0001006a /* RIGHT */ 77*4882a593Smuzhiyun 0x0101001c /* ENTER */ 78*4882a593Smuzhiyun 0x0201006c>; /* DOWN */ 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun gpio_keys: volume_keys@0 { 82*4882a593Smuzhiyun compatible = "gpio-keys"; 83*4882a593Smuzhiyun #address-cells = <1>; 84*4882a593Smuzhiyun #size-cells = <0>; 85*4882a593Smuzhiyun autorepeat; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun switch@9 { 88*4882a593Smuzhiyun label = "volume-up"; 89*4882a593Smuzhiyun linux,code = <115>; 90*4882a593Smuzhiyun gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 91*4882a593Smuzhiyun gpio-key,wakeup; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun switch@10 { 95*4882a593Smuzhiyun label = "volume-down"; 96*4882a593Smuzhiyun linux,code = <114>; 97*4882a593Smuzhiyun gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 98*4882a593Smuzhiyun gpio-key,wakeup; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun backlight { 103*4882a593Smuzhiyun compatible = "pwm-backlight"; 104*4882a593Smuzhiyun pwms = <&ecap0 0 50000 0>; 105*4882a593Smuzhiyun brightness-levels = <0 51 53 56 62 75 101 152 255>; 106*4882a593Smuzhiyun default-brightness-level = <8>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun panel { 110*4882a593Smuzhiyun compatible = "ti,tilcdc,panel"; 111*4882a593Smuzhiyun status = "okay"; 112*4882a593Smuzhiyun pinctrl-names = "default"; 113*4882a593Smuzhiyun pinctrl-0 = <&lcd_pins_s0>; 114*4882a593Smuzhiyun panel-info { 115*4882a593Smuzhiyun ac-bias = <255>; 116*4882a593Smuzhiyun ac-bias-intrpt = <0>; 117*4882a593Smuzhiyun dma-burst-sz = <16>; 118*4882a593Smuzhiyun bpp = <32>; 119*4882a593Smuzhiyun fdd = <0x80>; 120*4882a593Smuzhiyun sync-edge = <0>; 121*4882a593Smuzhiyun sync-ctrl = <1>; 122*4882a593Smuzhiyun raster-order = <0>; 123*4882a593Smuzhiyun fifo-th = <0>; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun display-timings { 127*4882a593Smuzhiyun 800x480p62 { 128*4882a593Smuzhiyun clock-frequency = <30000000>; 129*4882a593Smuzhiyun hactive = <800>; 130*4882a593Smuzhiyun vactive = <480>; 131*4882a593Smuzhiyun hfront-porch = <39>; 132*4882a593Smuzhiyun hback-porch = <39>; 133*4882a593Smuzhiyun hsync-len = <47>; 134*4882a593Smuzhiyun vback-porch = <29>; 135*4882a593Smuzhiyun vfront-porch = <13>; 136*4882a593Smuzhiyun vsync-len = <2>; 137*4882a593Smuzhiyun hsync-active = <1>; 138*4882a593Smuzhiyun vsync-active = <1>; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun sound { 144*4882a593Smuzhiyun compatible = "ti,da830-evm-audio"; 145*4882a593Smuzhiyun ti,model = "AM335x-EVM"; 146*4882a593Smuzhiyun ti,audio-codec = <&tlv320aic3106>; 147*4882a593Smuzhiyun ti,mcasp-controller = <&mcasp1>; 148*4882a593Smuzhiyun ti,codec-clock-rate = <12000000>; 149*4882a593Smuzhiyun ti,audio-routing = 150*4882a593Smuzhiyun "Headphone Jack", "HPLOUT", 151*4882a593Smuzhiyun "Headphone Jack", "HPROUT", 152*4882a593Smuzhiyun "LINE1L", "Line In", 153*4882a593Smuzhiyun "LINE1R", "Line In"; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun}; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun&am33xx_pinmux { 158*4882a593Smuzhiyun pinctrl-names = "default"; 159*4882a593Smuzhiyun pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun matrix_keypad_s0: matrix_keypad_s0 { 162*4882a593Smuzhiyun pinctrl-single,pins = < 163*4882a593Smuzhiyun 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ 164*4882a593Smuzhiyun 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ 165*4882a593Smuzhiyun 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ 166*4882a593Smuzhiyun 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ 167*4882a593Smuzhiyun 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ 168*4882a593Smuzhiyun >; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun volume_keys_s0: volume_keys_s0 { 172*4882a593Smuzhiyun pinctrl-single,pins = < 173*4882a593Smuzhiyun 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ 174*4882a593Smuzhiyun 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ 175*4882a593Smuzhiyun >; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun i2c0_pins: pinmux_i2c0_pins { 179*4882a593Smuzhiyun pinctrl-single,pins = < 180*4882a593Smuzhiyun 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 181*4882a593Smuzhiyun 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 182*4882a593Smuzhiyun >; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun i2c1_pins: pinmux_i2c1_pins { 186*4882a593Smuzhiyun pinctrl-single,pins = < 187*4882a593Smuzhiyun 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ 188*4882a593Smuzhiyun 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ 189*4882a593Smuzhiyun >; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun uart0_pins: pinmux_uart0_pins { 193*4882a593Smuzhiyun pinctrl-single,pins = < 194*4882a593Smuzhiyun 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 195*4882a593Smuzhiyun 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ 196*4882a593Smuzhiyun >; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun uart1_pins: pinmux_uart1_pins { 200*4882a593Smuzhiyun pinctrl-single,pins = < 201*4882a593Smuzhiyun 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ 202*4882a593Smuzhiyun 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ 203*4882a593Smuzhiyun 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ 204*4882a593Smuzhiyun 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ 205*4882a593Smuzhiyun >; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun clkout2_pin: pinmux_clkout2_pin { 209*4882a593Smuzhiyun pinctrl-single,pins = < 210*4882a593Smuzhiyun 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ 211*4882a593Smuzhiyun >; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun nandflash_pins_s0: nandflash_pins_s0 { 215*4882a593Smuzhiyun pinctrl-single,pins = < 216*4882a593Smuzhiyun 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 217*4882a593Smuzhiyun 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 218*4882a593Smuzhiyun 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 219*4882a593Smuzhiyun 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 220*4882a593Smuzhiyun 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 221*4882a593Smuzhiyun 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 222*4882a593Smuzhiyun 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 223*4882a593Smuzhiyun 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 224*4882a593Smuzhiyun 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 225*4882a593Smuzhiyun 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ 226*4882a593Smuzhiyun 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 227*4882a593Smuzhiyun 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 228*4882a593Smuzhiyun 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 229*4882a593Smuzhiyun 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 230*4882a593Smuzhiyun 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 231*4882a593Smuzhiyun >; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun ecap0_pins: backlight_pins { 235*4882a593Smuzhiyun pinctrl-single,pins = < 236*4882a593Smuzhiyun 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 237*4882a593Smuzhiyun >; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun cpsw_default: cpsw_default { 241*4882a593Smuzhiyun pinctrl-single,pins = < 242*4882a593Smuzhiyun /* Slave 1 */ 243*4882a593Smuzhiyun 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 244*4882a593Smuzhiyun 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 245*4882a593Smuzhiyun 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ 246*4882a593Smuzhiyun 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ 247*4882a593Smuzhiyun 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ 248*4882a593Smuzhiyun 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ 249*4882a593Smuzhiyun 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ 250*4882a593Smuzhiyun 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ 251*4882a593Smuzhiyun 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ 252*4882a593Smuzhiyun 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ 253*4882a593Smuzhiyun 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ 254*4882a593Smuzhiyun 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ 255*4882a593Smuzhiyun >; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun cpsw_sleep: cpsw_sleep { 259*4882a593Smuzhiyun pinctrl-single,pins = < 260*4882a593Smuzhiyun /* Slave 1 reset value */ 261*4882a593Smuzhiyun 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 262*4882a593Smuzhiyun 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) 263*4882a593Smuzhiyun 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) 264*4882a593Smuzhiyun 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) 265*4882a593Smuzhiyun 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 266*4882a593Smuzhiyun 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 267*4882a593Smuzhiyun 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) 268*4882a593Smuzhiyun 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) 269*4882a593Smuzhiyun 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) 270*4882a593Smuzhiyun 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) 271*4882a593Smuzhiyun 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 272*4882a593Smuzhiyun 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) 273*4882a593Smuzhiyun >; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun davinci_mdio_default: davinci_mdio_default { 277*4882a593Smuzhiyun pinctrl-single,pins = < 278*4882a593Smuzhiyun /* MDIO */ 279*4882a593Smuzhiyun 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 280*4882a593Smuzhiyun 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 281*4882a593Smuzhiyun >; 282*4882a593Smuzhiyun }; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun davinci_mdio_sleep: davinci_mdio_sleep { 285*4882a593Smuzhiyun pinctrl-single,pins = < 286*4882a593Smuzhiyun /* MDIO reset value */ 287*4882a593Smuzhiyun 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 288*4882a593Smuzhiyun 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 289*4882a593Smuzhiyun >; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun mmc1_pins: pinmux_mmc1_pins { 293*4882a593Smuzhiyun pinctrl-single,pins = < 294*4882a593Smuzhiyun 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 295*4882a593Smuzhiyun >; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun mmc3_pins: pinmux_mmc3_pins { 299*4882a593Smuzhiyun pinctrl-single,pins = < 300*4882a593Smuzhiyun 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ 301*4882a593Smuzhiyun 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ 302*4882a593Smuzhiyun 0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ 303*4882a593Smuzhiyun 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ 304*4882a593Smuzhiyun 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ 305*4882a593Smuzhiyun 0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ 306*4882a593Smuzhiyun >; 307*4882a593Smuzhiyun }; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun wlan_pins: pinmux_wlan_pins { 310*4882a593Smuzhiyun pinctrl-single,pins = < 311*4882a593Smuzhiyun 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */ 312*4882a593Smuzhiyun 0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ 313*4882a593Smuzhiyun 0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ 314*4882a593Smuzhiyun >; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun lcd_pins_s0: lcd_pins_s0 { 318*4882a593Smuzhiyun pinctrl-single,pins = < 319*4882a593Smuzhiyun 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ 320*4882a593Smuzhiyun 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ 321*4882a593Smuzhiyun 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ 322*4882a593Smuzhiyun 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ 323*4882a593Smuzhiyun 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ 324*4882a593Smuzhiyun 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ 325*4882a593Smuzhiyun 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ 326*4882a593Smuzhiyun 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ 327*4882a593Smuzhiyun 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ 328*4882a593Smuzhiyun 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ 329*4882a593Smuzhiyun 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ 330*4882a593Smuzhiyun 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ 331*4882a593Smuzhiyun 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ 332*4882a593Smuzhiyun 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ 333*4882a593Smuzhiyun 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ 334*4882a593Smuzhiyun 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ 335*4882a593Smuzhiyun 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ 336*4882a593Smuzhiyun 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ 337*4882a593Smuzhiyun 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ 338*4882a593Smuzhiyun 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ 339*4882a593Smuzhiyun 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ 340*4882a593Smuzhiyun 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ 341*4882a593Smuzhiyun 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ 342*4882a593Smuzhiyun 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ 343*4882a593Smuzhiyun 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ 344*4882a593Smuzhiyun 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ 345*4882a593Smuzhiyun 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ 346*4882a593Smuzhiyun 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ 347*4882a593Smuzhiyun >; 348*4882a593Smuzhiyun }; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun am335x_evm_audio_pins: am335x_evm_audio_pins { 351*4882a593Smuzhiyun pinctrl-single,pins = < 352*4882a593Smuzhiyun 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ 353*4882a593Smuzhiyun 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ 354*4882a593Smuzhiyun 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ 355*4882a593Smuzhiyun 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 356*4882a593Smuzhiyun >; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun dcan1_pins_default: dcan1_pins_default { 360*4882a593Smuzhiyun pinctrl-single,pins = < 361*4882a593Smuzhiyun 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ 362*4882a593Smuzhiyun 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ 363*4882a593Smuzhiyun >; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun}; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun&uart0 { 368*4882a593Smuzhiyun pinctrl-names = "default"; 369*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun status = "okay"; 372*4882a593Smuzhiyun}; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun&uart1 { 375*4882a593Smuzhiyun pinctrl-names = "default"; 376*4882a593Smuzhiyun pinctrl-0 = <&uart1_pins>; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun status = "okay"; 379*4882a593Smuzhiyun}; 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun&i2c0 { 382*4882a593Smuzhiyun pinctrl-names = "default"; 383*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun status = "okay"; 386*4882a593Smuzhiyun clock-frequency = <400000>; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun tps: tps@2d { 389*4882a593Smuzhiyun reg = <0x2d>; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun}; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun&usb { 394*4882a593Smuzhiyun status = "okay"; 395*4882a593Smuzhiyun}; 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun&usb_ctrl_mod { 398*4882a593Smuzhiyun status = "okay"; 399*4882a593Smuzhiyun}; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun&usb0_phy { 402*4882a593Smuzhiyun status = "okay"; 403*4882a593Smuzhiyun}; 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun&usb1_phy { 406*4882a593Smuzhiyun status = "okay"; 407*4882a593Smuzhiyun}; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun&usb0 { 410*4882a593Smuzhiyun status = "okay"; 411*4882a593Smuzhiyun}; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun&usb1 { 414*4882a593Smuzhiyun status = "okay"; 415*4882a593Smuzhiyun dr_mode = "host"; 416*4882a593Smuzhiyun}; 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun&cppi41dma { 419*4882a593Smuzhiyun status = "okay"; 420*4882a593Smuzhiyun}; 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun&i2c1 { 423*4882a593Smuzhiyun pinctrl-names = "default"; 424*4882a593Smuzhiyun pinctrl-0 = <&i2c1_pins>; 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun status = "okay"; 427*4882a593Smuzhiyun clock-frequency = <100000>; 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun lis331dlh: lis331dlh@18 { 430*4882a593Smuzhiyun compatible = "st,lis331dlh", "st,lis3lv02d"; 431*4882a593Smuzhiyun reg = <0x18>; 432*4882a593Smuzhiyun Vdd-supply = <&lis3_reg>; 433*4882a593Smuzhiyun Vdd_IO-supply = <&lis3_reg>; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun st,click-single-x; 436*4882a593Smuzhiyun st,click-single-y; 437*4882a593Smuzhiyun st,click-single-z; 438*4882a593Smuzhiyun st,click-thresh-x = <10>; 439*4882a593Smuzhiyun st,click-thresh-y = <10>; 440*4882a593Smuzhiyun st,click-thresh-z = <10>; 441*4882a593Smuzhiyun st,irq1-click; 442*4882a593Smuzhiyun st,irq2-click; 443*4882a593Smuzhiyun st,wakeup-x-lo; 444*4882a593Smuzhiyun st,wakeup-x-hi; 445*4882a593Smuzhiyun st,wakeup-y-lo; 446*4882a593Smuzhiyun st,wakeup-y-hi; 447*4882a593Smuzhiyun st,wakeup-z-lo; 448*4882a593Smuzhiyun st,wakeup-z-hi; 449*4882a593Smuzhiyun st,min-limit-x = <120>; 450*4882a593Smuzhiyun st,min-limit-y = <120>; 451*4882a593Smuzhiyun st,min-limit-z = <140>; 452*4882a593Smuzhiyun st,max-limit-x = <550>; 453*4882a593Smuzhiyun st,max-limit-y = <550>; 454*4882a593Smuzhiyun st,max-limit-z = <750>; 455*4882a593Smuzhiyun }; 456*4882a593Smuzhiyun 457*4882a593Smuzhiyun tsl2550: tsl2550@39 { 458*4882a593Smuzhiyun compatible = "taos,tsl2550"; 459*4882a593Smuzhiyun reg = <0x39>; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun tmp275: tmp275@48 { 463*4882a593Smuzhiyun compatible = "ti,tmp275"; 464*4882a593Smuzhiyun reg = <0x48>; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun tlv320aic3106: tlv320aic3106@1b { 468*4882a593Smuzhiyun compatible = "ti,tlv320aic3106"; 469*4882a593Smuzhiyun reg = <0x1b>; 470*4882a593Smuzhiyun status = "okay"; 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun /* Regulators */ 473*4882a593Smuzhiyun AVDD-supply = <&vaux2_reg>; 474*4882a593Smuzhiyun IOVDD-supply = <&vaux2_reg>; 475*4882a593Smuzhiyun DRVDD-supply = <&vaux2_reg>; 476*4882a593Smuzhiyun DVDD-supply = <&vbat>; 477*4882a593Smuzhiyun }; 478*4882a593Smuzhiyun}; 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun&lcdc { 481*4882a593Smuzhiyun status = "okay"; 482*4882a593Smuzhiyun}; 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun&elm { 485*4882a593Smuzhiyun status = "okay"; 486*4882a593Smuzhiyun}; 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun&epwmss0 { 489*4882a593Smuzhiyun status = "okay"; 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun ecap0: ecap@48300100 { 492*4882a593Smuzhiyun status = "okay"; 493*4882a593Smuzhiyun pinctrl-names = "default"; 494*4882a593Smuzhiyun pinctrl-0 = <&ecap0_pins>; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun}; 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun&gpmc { 499*4882a593Smuzhiyun status = "okay"; 500*4882a593Smuzhiyun pinctrl-names = "default"; 501*4882a593Smuzhiyun pinctrl-0 = <&nandflash_pins_s0>; 502*4882a593Smuzhiyun ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ 503*4882a593Smuzhiyun nand@0,0 { 504*4882a593Smuzhiyun reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 505*4882a593Smuzhiyun ti,nand-ecc-opt = "bch8"; 506*4882a593Smuzhiyun ti,elm-id = <&elm>; 507*4882a593Smuzhiyun nand-bus-width = <8>; 508*4882a593Smuzhiyun gpmc,device-width = <1>; 509*4882a593Smuzhiyun gpmc,sync-clk-ps = <0>; 510*4882a593Smuzhiyun gpmc,cs-on-ns = <0>; 511*4882a593Smuzhiyun gpmc,cs-rd-off-ns = <44>; 512*4882a593Smuzhiyun gpmc,cs-wr-off-ns = <44>; 513*4882a593Smuzhiyun gpmc,adv-on-ns = <6>; 514*4882a593Smuzhiyun gpmc,adv-rd-off-ns = <34>; 515*4882a593Smuzhiyun gpmc,adv-wr-off-ns = <44>; 516*4882a593Smuzhiyun gpmc,we-on-ns = <0>; 517*4882a593Smuzhiyun gpmc,we-off-ns = <40>; 518*4882a593Smuzhiyun gpmc,oe-on-ns = <0>; 519*4882a593Smuzhiyun gpmc,oe-off-ns = <54>; 520*4882a593Smuzhiyun gpmc,access-ns = <64>; 521*4882a593Smuzhiyun gpmc,rd-cycle-ns = <82>; 522*4882a593Smuzhiyun gpmc,wr-cycle-ns = <82>; 523*4882a593Smuzhiyun gpmc,wait-on-read = "true"; 524*4882a593Smuzhiyun gpmc,wait-on-write = "true"; 525*4882a593Smuzhiyun gpmc,bus-turnaround-ns = <0>; 526*4882a593Smuzhiyun gpmc,cycle2cycle-delay-ns = <0>; 527*4882a593Smuzhiyun gpmc,clk-activation-ns = <0>; 528*4882a593Smuzhiyun gpmc,wait-monitoring-ns = <0>; 529*4882a593Smuzhiyun gpmc,wr-access-ns = <40>; 530*4882a593Smuzhiyun gpmc,wr-data-mux-bus-ns = <0>; 531*4882a593Smuzhiyun /* MTD partition table */ 532*4882a593Smuzhiyun /* All SPL-* partitions are sized to minimal length 533*4882a593Smuzhiyun * which can be independently programmable. For 534*4882a593Smuzhiyun * NAND flash this is equal to size of erase-block */ 535*4882a593Smuzhiyun #address-cells = <1>; 536*4882a593Smuzhiyun #size-cells = <1>; 537*4882a593Smuzhiyun partition@0 { 538*4882a593Smuzhiyun label = "NAND.SPL"; 539*4882a593Smuzhiyun reg = <0x00000000 0x000020000>; 540*4882a593Smuzhiyun }; 541*4882a593Smuzhiyun partition@1 { 542*4882a593Smuzhiyun label = "NAND.SPL.backup1"; 543*4882a593Smuzhiyun reg = <0x00020000 0x00020000>; 544*4882a593Smuzhiyun }; 545*4882a593Smuzhiyun partition@2 { 546*4882a593Smuzhiyun label = "NAND.SPL.backup2"; 547*4882a593Smuzhiyun reg = <0x00040000 0x00020000>; 548*4882a593Smuzhiyun }; 549*4882a593Smuzhiyun partition@3 { 550*4882a593Smuzhiyun label = "NAND.SPL.backup3"; 551*4882a593Smuzhiyun reg = <0x00060000 0x00020000>; 552*4882a593Smuzhiyun }; 553*4882a593Smuzhiyun partition@4 { 554*4882a593Smuzhiyun label = "NAND.u-boot-spl-os"; 555*4882a593Smuzhiyun reg = <0x00080000 0x00040000>; 556*4882a593Smuzhiyun }; 557*4882a593Smuzhiyun partition@5 { 558*4882a593Smuzhiyun label = "NAND.u-boot"; 559*4882a593Smuzhiyun reg = <0x000C0000 0x00100000>; 560*4882a593Smuzhiyun }; 561*4882a593Smuzhiyun partition@6 { 562*4882a593Smuzhiyun label = "NAND.u-boot-env"; 563*4882a593Smuzhiyun reg = <0x001C0000 0x00020000>; 564*4882a593Smuzhiyun }; 565*4882a593Smuzhiyun partition@7 { 566*4882a593Smuzhiyun label = "NAND.u-boot-env.backup1"; 567*4882a593Smuzhiyun reg = <0x001E0000 0x00020000>; 568*4882a593Smuzhiyun }; 569*4882a593Smuzhiyun partition@8 { 570*4882a593Smuzhiyun label = "NAND.kernel"; 571*4882a593Smuzhiyun reg = <0x00200000 0x00800000>; 572*4882a593Smuzhiyun }; 573*4882a593Smuzhiyun partition@9 { 574*4882a593Smuzhiyun label = "NAND.file-system"; 575*4882a593Smuzhiyun reg = <0x00A00000 0x0F600000>; 576*4882a593Smuzhiyun }; 577*4882a593Smuzhiyun }; 578*4882a593Smuzhiyun}; 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun#include "tps65910.dtsi" 581*4882a593Smuzhiyun 582*4882a593Smuzhiyun&mcasp1 { 583*4882a593Smuzhiyun pinctrl-names = "default"; 584*4882a593Smuzhiyun pinctrl-0 = <&am335x_evm_audio_pins>; 585*4882a593Smuzhiyun 586*4882a593Smuzhiyun status = "okay"; 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun op-mode = <0>; /* MCASP_IIS_MODE */ 589*4882a593Smuzhiyun tdm-slots = <2>; 590*4882a593Smuzhiyun /* 4 serializers */ 591*4882a593Smuzhiyun serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 592*4882a593Smuzhiyun 0 0 1 2 593*4882a593Smuzhiyun >; 594*4882a593Smuzhiyun tx-num-evt = <32>; 595*4882a593Smuzhiyun rx-num-evt = <32>; 596*4882a593Smuzhiyun}; 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun&tps { 599*4882a593Smuzhiyun vcc1-supply = <&vbat>; 600*4882a593Smuzhiyun vcc2-supply = <&vbat>; 601*4882a593Smuzhiyun vcc3-supply = <&vbat>; 602*4882a593Smuzhiyun vcc4-supply = <&vbat>; 603*4882a593Smuzhiyun vcc5-supply = <&vbat>; 604*4882a593Smuzhiyun vcc6-supply = <&vbat>; 605*4882a593Smuzhiyun vcc7-supply = <&vbat>; 606*4882a593Smuzhiyun vccio-supply = <&vbat>; 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun regulators { 609*4882a593Smuzhiyun vrtc_reg: regulator@0 { 610*4882a593Smuzhiyun regulator-always-on; 611*4882a593Smuzhiyun }; 612*4882a593Smuzhiyun 613*4882a593Smuzhiyun vio_reg: regulator@1 { 614*4882a593Smuzhiyun regulator-always-on; 615*4882a593Smuzhiyun }; 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun vdd1_reg: regulator@2 { 618*4882a593Smuzhiyun /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 619*4882a593Smuzhiyun regulator-name = "vdd_mpu"; 620*4882a593Smuzhiyun regulator-min-microvolt = <912500>; 621*4882a593Smuzhiyun regulator-max-microvolt = <1312500>; 622*4882a593Smuzhiyun regulator-boot-on; 623*4882a593Smuzhiyun regulator-always-on; 624*4882a593Smuzhiyun }; 625*4882a593Smuzhiyun 626*4882a593Smuzhiyun vdd2_reg: regulator@3 { 627*4882a593Smuzhiyun /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 628*4882a593Smuzhiyun regulator-name = "vdd_core"; 629*4882a593Smuzhiyun regulator-min-microvolt = <912500>; 630*4882a593Smuzhiyun regulator-max-microvolt = <1150000>; 631*4882a593Smuzhiyun regulator-boot-on; 632*4882a593Smuzhiyun regulator-always-on; 633*4882a593Smuzhiyun }; 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun vdd3_reg: regulator@4 { 636*4882a593Smuzhiyun regulator-always-on; 637*4882a593Smuzhiyun }; 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun vdig1_reg: regulator@5 { 640*4882a593Smuzhiyun regulator-always-on; 641*4882a593Smuzhiyun }; 642*4882a593Smuzhiyun 643*4882a593Smuzhiyun vdig2_reg: regulator@6 { 644*4882a593Smuzhiyun regulator-always-on; 645*4882a593Smuzhiyun }; 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun vpll_reg: regulator@7 { 648*4882a593Smuzhiyun regulator-always-on; 649*4882a593Smuzhiyun }; 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun vdac_reg: regulator@8 { 652*4882a593Smuzhiyun regulator-always-on; 653*4882a593Smuzhiyun }; 654*4882a593Smuzhiyun 655*4882a593Smuzhiyun vaux1_reg: regulator@9 { 656*4882a593Smuzhiyun regulator-always-on; 657*4882a593Smuzhiyun }; 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun vaux2_reg: regulator@10 { 660*4882a593Smuzhiyun regulator-always-on; 661*4882a593Smuzhiyun }; 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun vaux33_reg: regulator@11 { 664*4882a593Smuzhiyun regulator-always-on; 665*4882a593Smuzhiyun }; 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun vmmc_reg: regulator@12 { 668*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 669*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 670*4882a593Smuzhiyun regulator-always-on; 671*4882a593Smuzhiyun }; 672*4882a593Smuzhiyun }; 673*4882a593Smuzhiyun}; 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun&mac { 676*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 677*4882a593Smuzhiyun pinctrl-0 = <&cpsw_default>; 678*4882a593Smuzhiyun pinctrl-1 = <&cpsw_sleep>; 679*4882a593Smuzhiyun status = "okay"; 680*4882a593Smuzhiyun}; 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun&davinci_mdio { 683*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 684*4882a593Smuzhiyun pinctrl-0 = <&davinci_mdio_default>; 685*4882a593Smuzhiyun pinctrl-1 = <&davinci_mdio_sleep>; 686*4882a593Smuzhiyun status = "okay"; 687*4882a593Smuzhiyun}; 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun&cpsw_emac0 { 690*4882a593Smuzhiyun phy_id = <&davinci_mdio>, <0>; 691*4882a593Smuzhiyun phy-mode = "rgmii-txid"; 692*4882a593Smuzhiyun}; 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun&cpsw_emac1 { 695*4882a593Smuzhiyun phy_id = <&davinci_mdio>, <1>; 696*4882a593Smuzhiyun phy-mode = "rgmii-txid"; 697*4882a593Smuzhiyun}; 698*4882a593Smuzhiyun 699*4882a593Smuzhiyun&tscadc { 700*4882a593Smuzhiyun status = "okay"; 701*4882a593Smuzhiyun tsc { 702*4882a593Smuzhiyun ti,wires = <4>; 703*4882a593Smuzhiyun ti,x-plate-resistance = <200>; 704*4882a593Smuzhiyun ti,coordinate-readouts = <5>; 705*4882a593Smuzhiyun ti,wire-config = <0x00 0x11 0x22 0x33>; 706*4882a593Smuzhiyun ti,charge-delay = <0x400>; 707*4882a593Smuzhiyun }; 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun adc { 710*4882a593Smuzhiyun ti,adc-channels = <4 5 6 7>; 711*4882a593Smuzhiyun }; 712*4882a593Smuzhiyun}; 713*4882a593Smuzhiyun 714*4882a593Smuzhiyun&mmc1 { 715*4882a593Smuzhiyun status = "okay"; 716*4882a593Smuzhiyun vmmc-supply = <&vmmc_reg>; 717*4882a593Smuzhiyun bus-width = <4>; 718*4882a593Smuzhiyun pinctrl-names = "default"; 719*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 720*4882a593Smuzhiyun cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 721*4882a593Smuzhiyun}; 722*4882a593Smuzhiyun 723*4882a593Smuzhiyun&mmc3 { 724*4882a593Smuzhiyun /* these are on the crossbar and are outlined in the 725*4882a593Smuzhiyun xbar-event-map element */ 726*4882a593Smuzhiyun dmas = <&edma 12 727*4882a593Smuzhiyun &edma 13>; 728*4882a593Smuzhiyun dma-names = "tx", "rx"; 729*4882a593Smuzhiyun status = "okay"; 730*4882a593Smuzhiyun vmmc-supply = <&wlan_en_reg>; 731*4882a593Smuzhiyun bus-width = <4>; 732*4882a593Smuzhiyun pinctrl-names = "default"; 733*4882a593Smuzhiyun pinctrl-0 = <&mmc3_pins &wlan_pins>; 734*4882a593Smuzhiyun ti,non-removable; 735*4882a593Smuzhiyun ti,needs-special-hs-handling; 736*4882a593Smuzhiyun cap-power-off-card; 737*4882a593Smuzhiyun keep-power-in-suspend; 738*4882a593Smuzhiyun 739*4882a593Smuzhiyun #address-cells = <1>; 740*4882a593Smuzhiyun #size-cells = <0>; 741*4882a593Smuzhiyun wlcore: wlcore@0 { 742*4882a593Smuzhiyun compatible = "ti,wl1835"; 743*4882a593Smuzhiyun reg = <2>; 744*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 745*4882a593Smuzhiyun interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 746*4882a593Smuzhiyun }; 747*4882a593Smuzhiyun}; 748*4882a593Smuzhiyun 749*4882a593Smuzhiyun&edma { 750*4882a593Smuzhiyun ti,edma-xbar-event-map = /bits/ 16 <1 12 751*4882a593Smuzhiyun 2 13>; 752*4882a593Smuzhiyun}; 753*4882a593Smuzhiyun 754*4882a593Smuzhiyun&sham { 755*4882a593Smuzhiyun status = "okay"; 756*4882a593Smuzhiyun}; 757*4882a593Smuzhiyun 758*4882a593Smuzhiyun&aes { 759*4882a593Smuzhiyun status = "okay"; 760*4882a593Smuzhiyun}; 761*4882a593Smuzhiyun 762*4882a593Smuzhiyun&dcan1 { 763*4882a593Smuzhiyun status = "disabled"; /* Enable only if Profile 1 is selected */ 764*4882a593Smuzhiyun pinctrl-names = "default"; 765*4882a593Smuzhiyun pinctrl-0 = <&dcan1_pins_default>; 766*4882a593Smuzhiyun}; 767