xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/am335x-draco.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Common support for Siemens Draco SOM (AM335x based)
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2013,2014 - Stefan Roese <sr@denx.de>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License
7*4882a593Smuzhiyun * version 2.  This program is licensed "as is" without any warranty of any
8*4882a593Smuzhiyun * kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	chosen {
13*4882a593Smuzhiyun		stdout-path = &uart0;
14*4882a593Smuzhiyun		tick-timer = &timer2;
15*4882a593Smuzhiyun	};
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	memory {
18*4882a593Smuzhiyun		device_type = "memory";
19*4882a593Smuzhiyun		reg = <0x80000000 0x08000000>; /* 128 MB */
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	ocp {
23*4882a593Smuzhiyun		uart0: serial@44e09000 {
24*4882a593Smuzhiyun			pinctrl-names = "default";
25*4882a593Smuzhiyun			pinctrl-0 = <&uart0_pins>;
26*4882a593Smuzhiyun			status = "okay";
27*4882a593Smuzhiyun		};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun		i2c0: i2c@44e0b000 {
30*4882a593Smuzhiyun			pinctrl-names = "default";
31*4882a593Smuzhiyun			pinctrl-0 = <&i2c0_pins>;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun			status = "okay";
34*4882a593Smuzhiyun			clock-frequency = <400000>;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun			eeprom: eeprom@50 {
37*4882a593Smuzhiyun				compatible = "atmel,24c128";
38*4882a593Smuzhiyun				reg = <0x50>;
39*4882a593Smuzhiyun				pagesize = <64>;
40*4882a593Smuzhiyun			};
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		musb: usb@47400000 {
44*4882a593Smuzhiyun			status = "okay";
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun			control@44e10620 {
47*4882a593Smuzhiyun				status = "okay";
48*4882a593Smuzhiyun			};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun			usb-phy@47401300 {
51*4882a593Smuzhiyun				status = "okay";
52*4882a593Smuzhiyun			};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun			usb-phy@47401b00 {
55*4882a593Smuzhiyun				status = "okay";
56*4882a593Smuzhiyun			};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun			usb@47401000 {
59*4882a593Smuzhiyun				status = "okay";
60*4882a593Smuzhiyun			};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun			usb@47401800 {
63*4882a593Smuzhiyun				status = "okay";
64*4882a593Smuzhiyun				dr_mode = "host";
65*4882a593Smuzhiyun			};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun			dma-controller@47402000  {
68*4882a593Smuzhiyun				status = "okay";
69*4882a593Smuzhiyun			};
70*4882a593Smuzhiyun		};
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun&am33xx_pinmux {
75*4882a593Smuzhiyun		i2c0_pins: pinmux_i2c0_pins {
76*4882a593Smuzhiyun			pinctrl-single,pins = <
77*4882a593Smuzhiyun				0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
78*4882a593Smuzhiyun				0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
79*4882a593Smuzhiyun			>;
80*4882a593Smuzhiyun		};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun		uart0_pins: pinmux_uart0_pins {
83*4882a593Smuzhiyun			pinctrl-single,pins = <
84*4882a593Smuzhiyun				0x170 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
85*4882a593Smuzhiyun				0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
86*4882a593Smuzhiyun			>;
87*4882a593Smuzhiyun		};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun		nandflash_pins: nandflash_pins {
90*4882a593Smuzhiyun			pinctrl-single,pins = <
91*4882a593Smuzhiyun				0x0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
92*4882a593Smuzhiyun				0x4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
93*4882a593Smuzhiyun				0x8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
94*4882a593Smuzhiyun				0xc (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
95*4882a593Smuzhiyun				0x10 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
96*4882a593Smuzhiyun				0x14 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
97*4882a593Smuzhiyun				0x18 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
98*4882a593Smuzhiyun				0x1c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
99*4882a593Smuzhiyun				0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
100*4882a593Smuzhiyun				0x74 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
101*4882a593Smuzhiyun				0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
102*4882a593Smuzhiyun				0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
103*4882a593Smuzhiyun				0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
104*4882a593Smuzhiyun				0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
105*4882a593Smuzhiyun				0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
106*4882a593Smuzhiyun			>;
107*4882a593Smuzhiyun		};
108*4882a593Smuzhiyun	};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun&timer3 {
112*4882a593Smuzhiyun	status = "disabled";
113*4882a593Smuzhiyun};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun&uart4 {
116*4882a593Smuzhiyun	status = "disabled";
117*4882a593Smuzhiyun};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun&elm {
120*4882a593Smuzhiyun	status = "okay";
121*4882a593Smuzhiyun};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun&gpmc {
124*4882a593Smuzhiyun	status = "okay";
125*4882a593Smuzhiyun	pinctrl-names = "default";
126*4882a593Smuzhiyun	pinctrl-0 = <&nandflash_pins>;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun	nand@0,0 {
131*4882a593Smuzhiyun		reg = <0 0 0>; /* CS0, offset 0 */
132*4882a593Smuzhiyun		nand-bus-width = <8>;
133*4882a593Smuzhiyun		ti,nand-ecc-opt = "bch8";
134*4882a593Smuzhiyun		gpmc,device-nand = "true";
135*4882a593Smuzhiyun		gpmc,device-width = <1>;
136*4882a593Smuzhiyun		gpmc,sync-clk-ps = <0>;
137*4882a593Smuzhiyun		gpmc,cs-on-ns = <0>;
138*4882a593Smuzhiyun		gpmc,cs-rd-off-ns = <44>;
139*4882a593Smuzhiyun		gpmc,cs-wr-off-ns = <44>;
140*4882a593Smuzhiyun		gpmc,adv-on-ns = <6>;
141*4882a593Smuzhiyun		gpmc,adv-rd-off-ns = <34>;
142*4882a593Smuzhiyun		gpmc,adv-wr-off-ns = <44>;
143*4882a593Smuzhiyun		gpmc,we-on-ns = <0>;
144*4882a593Smuzhiyun		gpmc,we-off-ns = <40>;
145*4882a593Smuzhiyun		gpmc,oe-on-ns = <0>;
146*4882a593Smuzhiyun		gpmc,oe-off-ns = <54>;
147*4882a593Smuzhiyun		gpmc,access-ns = <64>;
148*4882a593Smuzhiyun		gpmc,rd-cycle-ns = <82>;
149*4882a593Smuzhiyun		gpmc,wr-cycle-ns = <82>;
150*4882a593Smuzhiyun		gpmc,wait-on-read = "true";
151*4882a593Smuzhiyun		gpmc,wait-on-write = "true";
152*4882a593Smuzhiyun		gpmc,bus-turnaround-ns = <0>;
153*4882a593Smuzhiyun		gpmc,cycle2cycle-delay-ns = <0>;
154*4882a593Smuzhiyun		gpmc,clk-activation-ns = <0>;
155*4882a593Smuzhiyun		gpmc,wait-monitoring-ns = <0>;
156*4882a593Smuzhiyun		gpmc,wr-access-ns = <40>;
157*4882a593Smuzhiyun		gpmc,wr-data-mux-bus-ns = <0>;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun		#address-cells = <1>;
160*4882a593Smuzhiyun		#size-cells = <1>;
161*4882a593Smuzhiyun		elm_id = <&elm>;
162*4882a593Smuzhiyun	};
163*4882a593Smuzhiyun};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun/* disable the RTC node as its not accessible on the draco/dxr2 board */
166*4882a593Smuzhiyun&rtc {
167*4882a593Smuzhiyun	status = "disabled";
168*4882a593Smuzhiyun	ti,hwmods = "disabled";
169*4882a593Smuzhiyun};
170