xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/am335x-bone-common.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as
6*4882a593Smuzhiyun * published by the Free Software Foundation.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	cpus {
11*4882a593Smuzhiyun		cpu@0 {
12*4882a593Smuzhiyun			cpu0-supply = <&dcdc2_reg>;
13*4882a593Smuzhiyun		};
14*4882a593Smuzhiyun	};
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	chosen {
17*4882a593Smuzhiyun		stdout-path = &uart0;
18*4882a593Smuzhiyun		tick-timer = &timer2;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	memory {
22*4882a593Smuzhiyun		device_type = "memory";
23*4882a593Smuzhiyun		reg = <0x80000000 0x10000000>; /* 256 MB */
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	leds {
27*4882a593Smuzhiyun		pinctrl-names = "default";
28*4882a593Smuzhiyun		pinctrl-0 = <&user_leds_s0>;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun		compatible = "gpio-leds";
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun		led@2 {
33*4882a593Smuzhiyun			label = "beaglebone:green:heartbeat";
34*4882a593Smuzhiyun			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
35*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
36*4882a593Smuzhiyun			default-state = "off";
37*4882a593Smuzhiyun		};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun		led@3 {
40*4882a593Smuzhiyun			label = "beaglebone:green:mmc0";
41*4882a593Smuzhiyun			gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
42*4882a593Smuzhiyun			linux,default-trigger = "mmc0";
43*4882a593Smuzhiyun			default-state = "off";
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun		led@4 {
47*4882a593Smuzhiyun			label = "beaglebone:green:usr2";
48*4882a593Smuzhiyun			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
49*4882a593Smuzhiyun			linux,default-trigger = "cpu0";
50*4882a593Smuzhiyun			default-state = "off";
51*4882a593Smuzhiyun		};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun		led@5 {
54*4882a593Smuzhiyun			label = "beaglebone:green:usr3";
55*4882a593Smuzhiyun			gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
56*4882a593Smuzhiyun			linux,default-trigger = "mmc1";
57*4882a593Smuzhiyun			default-state = "off";
58*4882a593Smuzhiyun		};
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun	vmmcsd_fixed: fixedregulator@0 {
62*4882a593Smuzhiyun		compatible = "regulator-fixed";
63*4882a593Smuzhiyun		regulator-name = "vmmcsd_fixed";
64*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
65*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyun};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun&am33xx_pinmux {
70*4882a593Smuzhiyun	pinctrl-names = "default";
71*4882a593Smuzhiyun	pinctrl-0 = <&clkout2_pin>;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	user_leds_s0: user_leds_s0 {
74*4882a593Smuzhiyun		pinctrl-single,pins = <
75*4882a593Smuzhiyun			0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a5.gpio1_21 */
76*4882a593Smuzhiyun			0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_a6.gpio1_22 */
77*4882a593Smuzhiyun			0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a7.gpio1_23 */
78*4882a593Smuzhiyun			0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_a8.gpio1_24 */
79*4882a593Smuzhiyun		>;
80*4882a593Smuzhiyun	};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun	i2c0_pins: pinmux_i2c0_pins {
83*4882a593Smuzhiyun		pinctrl-single,pins = <
84*4882a593Smuzhiyun			0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
85*4882a593Smuzhiyun			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
86*4882a593Smuzhiyun		>;
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun	i2c2_pins: pinmux_i2c2_pins {
90*4882a593Smuzhiyun		pinctrl-single,pins = <
91*4882a593Smuzhiyun			0x178 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_ctsn.i2c2_sda */
92*4882a593Smuzhiyun			0x17c (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_rtsn.i2c2_scl */
93*4882a593Smuzhiyun		>;
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun	uart0_pins: pinmux_uart0_pins {
97*4882a593Smuzhiyun		pinctrl-single,pins = <
98*4882a593Smuzhiyun			0x170 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
99*4882a593Smuzhiyun			0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
100*4882a593Smuzhiyun		>;
101*4882a593Smuzhiyun	};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun	clkout2_pin: pinmux_clkout2_pin {
104*4882a593Smuzhiyun		pinctrl-single,pins = <
105*4882a593Smuzhiyun			0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* xdma_event_intr1.clkout2 */
106*4882a593Smuzhiyun		>;
107*4882a593Smuzhiyun	};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun	cpsw_default: cpsw_default {
110*4882a593Smuzhiyun		pinctrl-single,pins = <
111*4882a593Smuzhiyun			/* Slave 1 */
112*4882a593Smuzhiyun			0x110 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxerr.mii1_rxerr */
113*4882a593Smuzhiyun			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txen.mii1_txen */
114*4882a593Smuzhiyun			0x118 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxdv.mii1_rxdv */
115*4882a593Smuzhiyun			0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd3.mii1_txd3 */
116*4882a593Smuzhiyun			0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd2.mii1_txd2 */
117*4882a593Smuzhiyun			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd1.mii1_txd1 */
118*4882a593Smuzhiyun			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd0.mii1_txd0 */
119*4882a593Smuzhiyun			0x12c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_txclk.mii1_txclk */
120*4882a593Smuzhiyun			0x130 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxclk.mii1_rxclk */
121*4882a593Smuzhiyun			0x134 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd3.mii1_rxd3 */
122*4882a593Smuzhiyun			0x138 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd2.mii1_rxd2 */
123*4882a593Smuzhiyun			0x13c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd1.mii1_rxd1 */
124*4882a593Smuzhiyun			0x140 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd0.mii1_rxd0 */
125*4882a593Smuzhiyun		>;
126*4882a593Smuzhiyun	};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun	cpsw_sleep: cpsw_sleep {
129*4882a593Smuzhiyun		pinctrl-single,pins = <
130*4882a593Smuzhiyun			/* Slave 1 reset value */
131*4882a593Smuzhiyun			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132*4882a593Smuzhiyun			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
133*4882a593Smuzhiyun			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
134*4882a593Smuzhiyun			0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
135*4882a593Smuzhiyun			0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
136*4882a593Smuzhiyun			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
137*4882a593Smuzhiyun			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
138*4882a593Smuzhiyun			0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
139*4882a593Smuzhiyun			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
140*4882a593Smuzhiyun			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
141*4882a593Smuzhiyun			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
142*4882a593Smuzhiyun			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
143*4882a593Smuzhiyun			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
144*4882a593Smuzhiyun		>;
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun	davinci_mdio_default: davinci_mdio_default {
148*4882a593Smuzhiyun		pinctrl-single,pins = <
149*4882a593Smuzhiyun			/* MDIO */
150*4882a593Smuzhiyun			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
151*4882a593Smuzhiyun			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
152*4882a593Smuzhiyun		>;
153*4882a593Smuzhiyun	};
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun	davinci_mdio_sleep: davinci_mdio_sleep {
156*4882a593Smuzhiyun		pinctrl-single,pins = <
157*4882a593Smuzhiyun			/* MDIO reset value */
158*4882a593Smuzhiyun			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
159*4882a593Smuzhiyun			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
160*4882a593Smuzhiyun		>;
161*4882a593Smuzhiyun	};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun	mmc1_pins: pinmux_mmc1_pins {
164*4882a593Smuzhiyun		pinctrl-single,pins = <
165*4882a593Smuzhiyun			0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
166*4882a593Smuzhiyun		>;
167*4882a593Smuzhiyun	};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun	emmc_pins: pinmux_emmc_pins {
170*4882a593Smuzhiyun		pinctrl-single,pins = <
171*4882a593Smuzhiyun			0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
172*4882a593Smuzhiyun			0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
173*4882a593Smuzhiyun			0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
174*4882a593Smuzhiyun			0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
175*4882a593Smuzhiyun			0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
176*4882a593Smuzhiyun			0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
177*4882a593Smuzhiyun			0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
178*4882a593Smuzhiyun			0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
179*4882a593Smuzhiyun			0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
180*4882a593Smuzhiyun			0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
181*4882a593Smuzhiyun		>;
182*4882a593Smuzhiyun	};
183*4882a593Smuzhiyun};
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun&uart0 {
186*4882a593Smuzhiyun	pinctrl-names = "default";
187*4882a593Smuzhiyun	pinctrl-0 = <&uart0_pins>;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	status = "okay";
190*4882a593Smuzhiyun};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun&usb {
193*4882a593Smuzhiyun	status = "okay";
194*4882a593Smuzhiyun};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun&usb_ctrl_mod {
197*4882a593Smuzhiyun	status = "okay";
198*4882a593Smuzhiyun};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun&usb0_phy {
201*4882a593Smuzhiyun	status = "okay";
202*4882a593Smuzhiyun};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun&usb1_phy {
205*4882a593Smuzhiyun	status = "okay";
206*4882a593Smuzhiyun};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun&usb0 {
209*4882a593Smuzhiyun	status = "okay";
210*4882a593Smuzhiyun	dr_mode = "peripheral";
211*4882a593Smuzhiyun};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun&usb1 {
214*4882a593Smuzhiyun	status = "okay";
215*4882a593Smuzhiyun	dr_mode = "host";
216*4882a593Smuzhiyun};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun&cppi41dma  {
219*4882a593Smuzhiyun	status = "okay";
220*4882a593Smuzhiyun};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun&i2c0 {
223*4882a593Smuzhiyun	pinctrl-names = "default";
224*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins>;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun	status = "okay";
227*4882a593Smuzhiyun	clock-frequency = <400000>;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun	tps: tps@24 {
230*4882a593Smuzhiyun		reg = <0x24>;
231*4882a593Smuzhiyun	};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun	baseboard_eeprom: baseboard_eeprom@50 {
234*4882a593Smuzhiyun		compatible = "at,24c256";
235*4882a593Smuzhiyun		reg = <0x50>;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun		#address-cells = <1>;
238*4882a593Smuzhiyun		#size-cells = <1>;
239*4882a593Smuzhiyun		baseboard_data: baseboard_data@0 {
240*4882a593Smuzhiyun			reg = <0 0x100>;
241*4882a593Smuzhiyun		};
242*4882a593Smuzhiyun	};
243*4882a593Smuzhiyun};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun&i2c2 {
246*4882a593Smuzhiyun	pinctrl-names = "default";
247*4882a593Smuzhiyun	pinctrl-0 = <&i2c2_pins>;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun	status = "okay";
250*4882a593Smuzhiyun	clock-frequency = <100000>;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun	cape_eeprom0: cape_eeprom0@54 {
253*4882a593Smuzhiyun		compatible = "at,24c256";
254*4882a593Smuzhiyun		reg = <0x54>;
255*4882a593Smuzhiyun		#address-cells = <1>;
256*4882a593Smuzhiyun		#size-cells = <1>;
257*4882a593Smuzhiyun		cape0_data: cape_data@0 {
258*4882a593Smuzhiyun			reg = <0 0x100>;
259*4882a593Smuzhiyun		};
260*4882a593Smuzhiyun	};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun	cape_eeprom1: cape_eeprom1@55 {
263*4882a593Smuzhiyun		compatible = "at,24c256";
264*4882a593Smuzhiyun		reg = <0x55>;
265*4882a593Smuzhiyun		#address-cells = <1>;
266*4882a593Smuzhiyun		#size-cells = <1>;
267*4882a593Smuzhiyun		cape1_data: cape_data@0 {
268*4882a593Smuzhiyun			reg = <0 0x100>;
269*4882a593Smuzhiyun		};
270*4882a593Smuzhiyun	};
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun	cape_eeprom2: cape_eeprom2@56 {
273*4882a593Smuzhiyun		compatible = "at,24c256";
274*4882a593Smuzhiyun		reg = <0x56>;
275*4882a593Smuzhiyun		#address-cells = <1>;
276*4882a593Smuzhiyun		#size-cells = <1>;
277*4882a593Smuzhiyun		cape2_data: cape_data@0 {
278*4882a593Smuzhiyun			reg = <0 0x100>;
279*4882a593Smuzhiyun		};
280*4882a593Smuzhiyun	};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun	cape_eeprom3: cape_eeprom3@57 {
283*4882a593Smuzhiyun		compatible = "at,24c256";
284*4882a593Smuzhiyun		reg = <0x57>;
285*4882a593Smuzhiyun		#address-cells = <1>;
286*4882a593Smuzhiyun		#size-cells = <1>;
287*4882a593Smuzhiyun		cape3_data: cape_data@0 {
288*4882a593Smuzhiyun			reg = <0 0x100>;
289*4882a593Smuzhiyun		};
290*4882a593Smuzhiyun	};
291*4882a593Smuzhiyun};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun/include/ "tps65217.dtsi"
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun&tps {
297*4882a593Smuzhiyun	/*
298*4882a593Smuzhiyun	 * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
299*4882a593Smuzhiyun	 * mode") at poweroff.  Most BeagleBone versions do not support RTC-only
300*4882a593Smuzhiyun	 * mode and risk hardware damage if this mode is entered.
301*4882a593Smuzhiyun	 *
302*4882a593Smuzhiyun	 * For details, see linux-omap mailing list May 2015 thread
303*4882a593Smuzhiyun	 *	[PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
304*4882a593Smuzhiyun	 * In particular, messages:
305*4882a593Smuzhiyun	 *	http://www.spinics.net/lists/linux-omap/msg118585.html
306*4882a593Smuzhiyun	 *	http://www.spinics.net/lists/linux-omap/msg118615.html
307*4882a593Smuzhiyun	 *
308*4882a593Smuzhiyun	 * You can override this later with
309*4882a593Smuzhiyun	 *	&tps {  /delete-property/ ti,pmic-shutdown-controller;  }
310*4882a593Smuzhiyun	 * if you want to use RTC-only mode and made sure you are not affected
311*4882a593Smuzhiyun	 * by the hardware problems. (Tip: double-check by performing a current
312*4882a593Smuzhiyun	 * measurement after shutdown: it should be less than 1 mA.)
313*4882a593Smuzhiyun	 */
314*4882a593Smuzhiyun	ti,pmic-shutdown-controller;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun	regulators {
317*4882a593Smuzhiyun		dcdc1_reg: regulator@0 {
318*4882a593Smuzhiyun			regulator-name = "vdds_dpr";
319*4882a593Smuzhiyun			regulator-always-on;
320*4882a593Smuzhiyun		};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun		dcdc2_reg: regulator@1 {
323*4882a593Smuzhiyun			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
324*4882a593Smuzhiyun			regulator-name = "vdd_mpu";
325*4882a593Smuzhiyun			regulator-min-microvolt = <925000>;
326*4882a593Smuzhiyun			regulator-max-microvolt = <1325000>;
327*4882a593Smuzhiyun			regulator-boot-on;
328*4882a593Smuzhiyun			regulator-always-on;
329*4882a593Smuzhiyun		};
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun		dcdc3_reg: regulator@2 {
332*4882a593Smuzhiyun			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
333*4882a593Smuzhiyun			regulator-name = "vdd_core";
334*4882a593Smuzhiyun			regulator-min-microvolt = <925000>;
335*4882a593Smuzhiyun			regulator-max-microvolt = <1150000>;
336*4882a593Smuzhiyun			regulator-boot-on;
337*4882a593Smuzhiyun			regulator-always-on;
338*4882a593Smuzhiyun		};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun		ldo1_reg: regulator@3 {
341*4882a593Smuzhiyun			regulator-name = "vio,vrtc,vdds";
342*4882a593Smuzhiyun			regulator-always-on;
343*4882a593Smuzhiyun		};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun		ldo2_reg: regulator@4 {
346*4882a593Smuzhiyun			regulator-name = "vdd_3v3aux";
347*4882a593Smuzhiyun			regulator-always-on;
348*4882a593Smuzhiyun		};
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun		ldo3_reg: regulator@5 {
351*4882a593Smuzhiyun			regulator-name = "vdd_1v8";
352*4882a593Smuzhiyun			regulator-always-on;
353*4882a593Smuzhiyun		};
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun		ldo4_reg: regulator@6 {
356*4882a593Smuzhiyun			regulator-name = "vdd_3v3a";
357*4882a593Smuzhiyun			regulator-always-on;
358*4882a593Smuzhiyun		};
359*4882a593Smuzhiyun	};
360*4882a593Smuzhiyun};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun&cpsw_emac0 {
363*4882a593Smuzhiyun	phy_id = <&davinci_mdio>, <0>;
364*4882a593Smuzhiyun	phy-mode = "mii";
365*4882a593Smuzhiyun};
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun&cpsw_emac1 {
368*4882a593Smuzhiyun	phy_id = <&davinci_mdio>, <1>;
369*4882a593Smuzhiyun	phy-mode = "mii";
370*4882a593Smuzhiyun};
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun&mac {
373*4882a593Smuzhiyun	pinctrl-names = "default", "sleep";
374*4882a593Smuzhiyun	pinctrl-0 = <&cpsw_default>;
375*4882a593Smuzhiyun	pinctrl-1 = <&cpsw_sleep>;
376*4882a593Smuzhiyun	status = "okay";
377*4882a593Smuzhiyun};
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun&davinci_mdio {
380*4882a593Smuzhiyun	pinctrl-names = "default", "sleep";
381*4882a593Smuzhiyun	pinctrl-0 = <&davinci_mdio_default>;
382*4882a593Smuzhiyun	pinctrl-1 = <&davinci_mdio_sleep>;
383*4882a593Smuzhiyun	status = "okay";
384*4882a593Smuzhiyun};
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun&mmc1 {
387*4882a593Smuzhiyun	status = "okay";
388*4882a593Smuzhiyun	bus-width = <0x4>;
389*4882a593Smuzhiyun	pinctrl-names = "default";
390*4882a593Smuzhiyun	pinctrl-0 = <&mmc1_pins>;
391*4882a593Smuzhiyun	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
392*4882a593Smuzhiyun};
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun&aes {
395*4882a593Smuzhiyun	status = "okay";
396*4882a593Smuzhiyun};
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun&sham {
399*4882a593Smuzhiyun	status = "okay";
400*4882a593Smuzhiyun};
401