1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * armboot - Startup Code for SA1100 CPU 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5*4882a593Smuzhiyun * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6*4882a593Smuzhiyun * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7*4882a593Smuzhiyun * Copyright (c) 2001 Alex Züpke <azu@sysgo.de> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include <asm-offsets.h> 13*4882a593Smuzhiyun#include <config.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/* 16*4882a593Smuzhiyun ************************************************************************* 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * Startup Code (reset vector) 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * do important init only if we don't start from memory! 21*4882a593Smuzhiyun * relocate armboot to ram 22*4882a593Smuzhiyun * setup stack 23*4882a593Smuzhiyun * jump to second stage 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun ************************************************************************* 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun .globl reset 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunreset: 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * set the cpu to SVC32 mode 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun mrs r0,cpsr 35*4882a593Smuzhiyun bic r0,r0,#0x1f 36*4882a593Smuzhiyun orr r0,r0,#0xd3 37*4882a593Smuzhiyun msr cpsr,r0 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * we do sys-critical inits only at reboot, 41*4882a593Smuzhiyun * not when booting from ram! 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun#ifndef CONFIG_SKIP_LOWLEVEL_INIT 44*4882a593Smuzhiyun bl cpu_init_crit 45*4882a593Smuzhiyun#endif 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun bl _main 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun/*------------------------------------------------------------------------------*/ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun .globl c_runtime_cpu_setup 52*4882a593Smuzhiyunc_runtime_cpu_setup: 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun mov pc, lr 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun/* 57*4882a593Smuzhiyun ************************************************************************* 58*4882a593Smuzhiyun * 59*4882a593Smuzhiyun * CPU_init_critical registers 60*4882a593Smuzhiyun * 61*4882a593Smuzhiyun * setup important registers 62*4882a593Smuzhiyun * setup memory timing 63*4882a593Smuzhiyun * 64*4882a593Smuzhiyun ************************************************************************* 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun/* Interrupt-Controller base address */ 69*4882a593SmuzhiyunIC_BASE: .word 0x90050000 70*4882a593Smuzhiyun#define ICMR 0x04 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun/* Reset-Controller */ 74*4882a593SmuzhiyunRST_BASE: .word 0x90030000 75*4882a593Smuzhiyun#define RSRR 0x00 76*4882a593Smuzhiyun#define RCSR 0x04 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun/* PWR */ 80*4882a593SmuzhiyunPWR_BASE: .word 0x90020000 81*4882a593Smuzhiyun#define PSPR 0x08 82*4882a593Smuzhiyun#define PPCR 0x14 83*4882a593Smuzhiyuncpuspeed: .word CONFIG_SYS_CPUSPEED 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun 86*4882a593Smuzhiyuncpu_init_crit: 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * mask all IRQs 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun ldr r0, IC_BASE 91*4882a593Smuzhiyun mov r1, #0x00 92*4882a593Smuzhiyun str r1, [r0, #ICMR] 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* set clock speed */ 95*4882a593Smuzhiyun ldr r0, PWR_BASE 96*4882a593Smuzhiyun ldr r1, cpuspeed 97*4882a593Smuzhiyun str r1, [r0, #PPCR] 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * before relocating, we have to setup RAM timing 102*4882a593Smuzhiyun * because memory timing is board-dependend, you will 103*4882a593Smuzhiyun * find a lowlevel_init.S in your board directory. 104*4882a593Smuzhiyun */ 105*4882a593Smuzhiyun mov ip, lr 106*4882a593Smuzhiyun bl lowlevel_init 107*4882a593Smuzhiyun mov lr, ip 108*4882a593Smuzhiyun#endif 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* 111*4882a593Smuzhiyun * disable MMU stuff and enable I-cache 112*4882a593Smuzhiyun */ 113*4882a593Smuzhiyun mrc p15,0,r0,c1,c0 114*4882a593Smuzhiyun bic r0, r0, #0x00002000 @ clear bit 13 (X) 115*4882a593Smuzhiyun bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) 116*4882a593Smuzhiyun orr r0, r0, #0x00001000 @ set bit 12 (I) Icache 117*4882a593Smuzhiyun orr r0, r0, #0x00000002 @ set bit 1 (A) Align 118*4882a593Smuzhiyun mcr p15,0,r0,c1,c0 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* 121*4882a593Smuzhiyun * flush v4 I/D caches 122*4882a593Smuzhiyun */ 123*4882a593Smuzhiyun mov r0, #0 124*4882a593Smuzhiyun mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 125*4882a593Smuzhiyun mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun mov pc, lr 128