1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2006
3*4882a593Smuzhiyun * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
11*4882a593Smuzhiyun # if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <asm/arch/pxa-regs.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun #include <usb.h>
16*4882a593Smuzhiyun
usb_cpu_init(void)17*4882a593Smuzhiyun int usb_cpu_init(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun #if defined(CONFIG_CPU_MONAHANS)
20*4882a593Smuzhiyun /* Enable USB host clock. */
21*4882a593Smuzhiyun writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
22*4882a593Smuzhiyun udelay(100);
23*4882a593Smuzhiyun #endif
24*4882a593Smuzhiyun #if defined(CONFIG_CPU_PXA27X)
25*4882a593Smuzhiyun /* Enable USB host clock. */
26*4882a593Smuzhiyun writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
27*4882a593Smuzhiyun #endif
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #if defined(CONFIG_CPU_MONAHANS)
30*4882a593Smuzhiyun /* Configure Port 2 for Host (USB Client Registers) */
31*4882a593Smuzhiyun writel(0x3000c, UP2OCR);
32*4882a593Smuzhiyun #endif
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
35*4882a593Smuzhiyun mdelay(11);
36*4882a593Smuzhiyun writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
39*4882a593Smuzhiyun while (readl(UHCHR) & UHCHR_FSBIR)
40*4882a593Smuzhiyun udelay(1);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
43*4882a593Smuzhiyun writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
44*4882a593Smuzhiyun #endif
45*4882a593Smuzhiyun #if defined(CONFIG_CPU_PXA27X)
46*4882a593Smuzhiyun writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
47*4882a593Smuzhiyun #endif
48*4882a593Smuzhiyun writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun return 0;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
usb_cpu_stop(void)53*4882a593Smuzhiyun int usb_cpu_stop(void)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
56*4882a593Smuzhiyun udelay(11);
57*4882a593Smuzhiyun writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
60*4882a593Smuzhiyun udelay(10);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
63*4882a593Smuzhiyun writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
64*4882a593Smuzhiyun #endif
65*4882a593Smuzhiyun #if defined(CONFIG_CPU_PXA27X)
66*4882a593Smuzhiyun writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
67*4882a593Smuzhiyun #endif
68*4882a593Smuzhiyun writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #if defined(CONFIG_CPU_MONAHANS)
71*4882a593Smuzhiyun /* Disable USB host clock. */
72*4882a593Smuzhiyun writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
73*4882a593Smuzhiyun udelay(100);
74*4882a593Smuzhiyun #endif
75*4882a593Smuzhiyun #if defined(CONFIG_CPU_PXA27X)
76*4882a593Smuzhiyun /* Disable USB host clock. */
77*4882a593Smuzhiyun writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
78*4882a593Smuzhiyun #endif
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return 0;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
usb_cpu_init_fail(void)83*4882a593Smuzhiyun int usb_cpu_init_fail(void)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun return usb_cpu_stop();
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun # endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
89*4882a593Smuzhiyun #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
90