1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2016 - 2017 Xilinx, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/arch/hardware.h>
12*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /*
15*4882a593Smuzhiyun * atfhandoffparams
16*4882a593Smuzhiyun * Parameter bitfield encoding
17*4882a593Smuzhiyun * -----------------------------------------------------------------------------
18*4882a593Smuzhiyun * Exec State 0 0 -> Aarch64, 1-> Aarch32
19*4882a593Smuzhiyun * endianness 1 0 -> LE, 1 -> BE
20*4882a593Smuzhiyun * secure (TZ) 2 0 -> Non secure, 1 -> secure
21*4882a593Smuzhiyun * EL 3:4 00 -> EL0, 01 -> EL1, 10 -> EL2, 11 -> EL3
22*4882a593Smuzhiyun * CPU# 5:6 00 -> A53_0, 01 -> A53_1, 10 -> A53_2, 11 -> A53_3
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define FSBL_FLAGS_ESTATE_SHIFT 0
26*4882a593Smuzhiyun #define FSBL_FLAGS_ESTATE_MASK (1 << FSBL_FLAGS_ESTATE_SHIFT)
27*4882a593Smuzhiyun #define FSBL_FLAGS_ESTATE_A64 0
28*4882a593Smuzhiyun #define FSBL_FLAGS_ESTATE_A32 1
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define FSBL_FLAGS_ENDIAN_SHIFT 1
31*4882a593Smuzhiyun #define FSBL_FLAGS_ENDIAN_MASK (1 << FSBL_FLAGS_ENDIAN_SHIFT)
32*4882a593Smuzhiyun #define FSBL_FLAGS_ENDIAN_LE 0
33*4882a593Smuzhiyun #define FSBL_FLAGS_ENDIAN_BE 1
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define FSBL_FLAGS_TZ_SHIFT 2
36*4882a593Smuzhiyun #define FSBL_FLAGS_TZ_MASK (1 << FSBL_FLAGS_TZ_SHIFT)
37*4882a593Smuzhiyun #define FSBL_FLAGS_NON_SECURE 0
38*4882a593Smuzhiyun #define FSBL_FLAGS_SECURE 1
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define FSBL_FLAGS_EL_SHIFT 3
41*4882a593Smuzhiyun #define FSBL_FLAGS_EL_MASK (3 << FSBL_FLAGS_EL_SHIFT)
42*4882a593Smuzhiyun #define FSBL_FLAGS_EL0 0
43*4882a593Smuzhiyun #define FSBL_FLAGS_EL1 1
44*4882a593Smuzhiyun #define FSBL_FLAGS_EL2 2
45*4882a593Smuzhiyun #define FSBL_FLAGS_EL3 3
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define FSBL_FLAGS_CPU_SHIFT 5
48*4882a593Smuzhiyun #define FSBL_FLAGS_CPU_MASK (3 << FSBL_FLAGS_CPU_SHIFT)
49*4882a593Smuzhiyun #define FSBL_FLAGS_A53_0 0
50*4882a593Smuzhiyun #define FSBL_FLAGS_A53_1 1
51*4882a593Smuzhiyun #define FSBL_FLAGS_A53_2 2
52*4882a593Smuzhiyun #define FSBL_FLAGS_A53_3 3
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define FSBL_MAX_PARTITIONS 8
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Structure corresponding to each partition entry */
57*4882a593Smuzhiyun struct xfsbl_partition {
58*4882a593Smuzhiyun uint64_t entry_point;
59*4882a593Smuzhiyun uint64_t flags;
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Structure for handoff parameters to ARM Trusted Firmware (ATF) */
63*4882a593Smuzhiyun struct xfsbl_atf_handoff_params {
64*4882a593Smuzhiyun uint8_t magic[4];
65*4882a593Smuzhiyun uint32_t num_entries;
66*4882a593Smuzhiyun struct xfsbl_partition partition[FSBL_MAX_PARTITIONS];
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #ifdef CONFIG_SPL_OS_BOOT
handoff_setup(void)70*4882a593Smuzhiyun void handoff_setup(void)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun struct xfsbl_atf_handoff_params *atfhandoffparams;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun atfhandoffparams = (void *)CONFIG_SPL_TEXT_BASE;
75*4882a593Smuzhiyun atfhandoffparams->magic[0] = 'X';
76*4882a593Smuzhiyun atfhandoffparams->magic[1] = 'L';
77*4882a593Smuzhiyun atfhandoffparams->magic[2] = 'N';
78*4882a593Smuzhiyun atfhandoffparams->magic[3] = 'X';
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun atfhandoffparams->num_entries = 1;
81*4882a593Smuzhiyun atfhandoffparams->partition[0].entry_point = CONFIG_SYS_TEXT_BASE;
82*4882a593Smuzhiyun atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 <<
83*4882a593Smuzhiyun FSBL_FLAGS_EL_SHIFT;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun writel(CONFIG_SPL_TEXT_BASE, &pmu_base->gen_storage6);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun #endif
88