1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2014 - 2015 Xilinx, Inc. 3*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <asm/arch/clk.h> 10*4882a593Smuzhiyun #include <asm/arch/hardware.h> 11*4882a593Smuzhiyun #include <asm/arch/sys_proto.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 14*4882a593Smuzhiyun zynqmp_get_system_timer_freq(void)15*4882a593Smuzhiyununsigned long zynqmp_get_system_timer_freq(void) 16*4882a593Smuzhiyun { 17*4882a593Smuzhiyun u32 ver = zynqmp_get_silicon_version(); 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun switch (ver) { 20*4882a593Smuzhiyun case ZYNQMP_CSU_VERSION_VELOCE: 21*4882a593Smuzhiyun return 10000; 22*4882a593Smuzhiyun case ZYNQMP_CSU_VERSION_EP108: 23*4882a593Smuzhiyun return 4000000; 24*4882a593Smuzhiyun case ZYNQMP_CSU_VERSION_QEMU: 25*4882a593Smuzhiyun return 50000000; 26*4882a593Smuzhiyun } 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun return 100000000; 29*4882a593Smuzhiyun } 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #ifdef CONFIG_CLOCKS 32*4882a593Smuzhiyun /** 33*4882a593Smuzhiyun * set_cpu_clk_info() - Initialize clock framework 34*4882a593Smuzhiyun * Always returns zero. 35*4882a593Smuzhiyun * 36*4882a593Smuzhiyun * This function is called from common code after relocation and sets up the 37*4882a593Smuzhiyun * clock framework. The framework must not be used before this function had been 38*4882a593Smuzhiyun * called. 39*4882a593Smuzhiyun */ set_cpu_clk_info(void)40*4882a593Smuzhiyunint set_cpu_clk_info(void) 41*4882a593Smuzhiyun { 42*4882a593Smuzhiyun gd->cpu_clk = get_tbclk(); 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Support Veloce to show at least 1MHz via bdi */ 45*4882a593Smuzhiyun if (gd->cpu_clk > 1000000) 46*4882a593Smuzhiyun gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; 47*4882a593Smuzhiyun else 48*4882a593Smuzhiyun gd->bd->bi_arm_freq = 1; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun gd->bd->bi_dsp_freq = 0; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun return 0; 53*4882a593Smuzhiyun } 54*4882a593Smuzhiyun #endif 55