1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * (C) Copyright 2013 3*4882a593Smuzhiyun * David Feng <fenghua@phytium.com.cn> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2002 6*4882a593Smuzhiyun * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * (C) Copyright 2010 9*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 10*4882a593Smuzhiyun * Aneesh V <aneesh@ti.com> 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunMEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, 16*4882a593Smuzhiyun LENGTH = CONFIG_SPL_MAX_SIZE } 17*4882a593SmuzhiyunMEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, 18*4882a593Smuzhiyun LENGTH = CONFIG_SPL_BSS_MAX_SIZE } 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") 21*4882a593SmuzhiyunOUTPUT_ARCH(aarch64) 22*4882a593SmuzhiyunENTRY(_start) 23*4882a593SmuzhiyunSECTIONS 24*4882a593Smuzhiyun{ 25*4882a593Smuzhiyun .text : { 26*4882a593Smuzhiyun . = ALIGN(8); 27*4882a593Smuzhiyun *(.__image_copy_start) 28*4882a593Smuzhiyun CPUDIR/start.o (.text*) 29*4882a593Smuzhiyun *(.text*) 30*4882a593Smuzhiyun } >.sram 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun .rodata : { 33*4882a593Smuzhiyun . = ALIGN(8); 34*4882a593Smuzhiyun *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) 35*4882a593Smuzhiyun } >.sram 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun .data : { 38*4882a593Smuzhiyun . = ALIGN(8); 39*4882a593Smuzhiyun *(.data*) 40*4882a593Smuzhiyun } >.sram 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun .u_boot_list : { 43*4882a593Smuzhiyun . = ALIGN(8); 44*4882a593Smuzhiyun KEEP(*(SORT(.u_boot_list*))); 45*4882a593Smuzhiyun } >.sram 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun .image_copy_end : { 48*4882a593Smuzhiyun . = ALIGN(8); 49*4882a593Smuzhiyun *(.__image_copy_end) 50*4882a593Smuzhiyun } >.sram 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun .end : { 53*4882a593Smuzhiyun . = ALIGN(8); 54*4882a593Smuzhiyun *(.__end) 55*4882a593Smuzhiyun } >.sram 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun#ifndef CONFIG_SPL_SKIP_RELOCATE 58*4882a593Smuzhiyun . = ALIGN(8); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun .rel_dyn_start : 61*4882a593Smuzhiyun { 62*4882a593Smuzhiyun *(.__rel_dyn_start) 63*4882a593Smuzhiyun } >.sram 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun .rela.dyn : { 66*4882a593Smuzhiyun *(.rela*) 67*4882a593Smuzhiyun } >.sram 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun .rel_dyn_end : 70*4882a593Smuzhiyun { 71*4882a593Smuzhiyun *(.__rel_dyn_end) 72*4882a593Smuzhiyun } >.sram 73*4882a593Smuzhiyun#endif 74*4882a593Smuzhiyun _image_binary_end = .; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun .bss_start (NOLOAD) : { 77*4882a593Smuzhiyun . = ALIGN(8); 78*4882a593Smuzhiyun KEEP(*(.__bss_start)); 79*4882a593Smuzhiyun } >.sdram 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun .bss (NOLOAD) : { 82*4882a593Smuzhiyun *(.bss*) 83*4882a593Smuzhiyun . = ALIGN(8); 84*4882a593Smuzhiyun } >.sdram 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun .bss_end (NOLOAD) : { 87*4882a593Smuzhiyun KEEP(*(.__bss_end)); 88*4882a593Smuzhiyun } >.sdram 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /DISCARD/ : { *(.dynsym) } 91*4882a593Smuzhiyun /DISCARD/ : { *(.dynstr*) } 92*4882a593Smuzhiyun /DISCARD/ : { *(.dynamic*) } 93*4882a593Smuzhiyun /DISCARD/ : { *(.plt*) } 94*4882a593Smuzhiyun /DISCARD/ : { *(.interp*) } 95*4882a593Smuzhiyun /DISCARD/ : { *(.gnu*) } 96*4882a593Smuzhiyun} 97