1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <asm/system.h>
10*4882a593Smuzhiyun #include <asm/armv8/mmu.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/arch/mc_me_regs.h>
13*4882a593Smuzhiyun #include "cpu.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
cpu_mask(void)17*4882a593Smuzhiyun u32 cpu_mask(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun return readl(MC_ME_CS);
20*4882a593Smuzhiyun }
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #ifndef CONFIG_SYS_DCACHE_OFF
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define S32V234_IRAM_BASE 0x3e800000UL
25*4882a593Smuzhiyun #define S32V234_IRAM_SIZE 0x800000UL
26*4882a593Smuzhiyun #define S32V234_DRAM_BASE1 0x80000000UL
27*4882a593Smuzhiyun #define S32V234_DRAM_SIZE1 0x40000000UL
28*4882a593Smuzhiyun #define S32V234_DRAM_BASE2 0xC0000000UL
29*4882a593Smuzhiyun #define S32V234_DRAM_SIZE2 0x20000000UL
30*4882a593Smuzhiyun #define S32V234_PERIPH_BASE 0x40000000UL
31*4882a593Smuzhiyun #define S32V234_PERIPH_SIZE 0x40000000UL
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static struct mm_region s32v234_mem_map[] = {
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun .virt = S32V234_IRAM_BASE,
36*4882a593Smuzhiyun .phys = S32V234_IRAM_BASE,
37*4882a593Smuzhiyun .size = S32V234_IRAM_SIZE,
38*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
39*4882a593Smuzhiyun PTE_BLOCK_OUTER_SHARE
40*4882a593Smuzhiyun }, {
41*4882a593Smuzhiyun .virt = S32V234_DRAM_BASE1,
42*4882a593Smuzhiyun .phys = S32V234_DRAM_BASE1,
43*4882a593Smuzhiyun .size = S32V234_DRAM_SIZE1,
44*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
45*4882a593Smuzhiyun PTE_BLOCK_OUTER_SHARE
46*4882a593Smuzhiyun }, {
47*4882a593Smuzhiyun .virt = S32V234_PERIPH_BASE,
48*4882a593Smuzhiyun .phys = S32V234_PERIPH_BASE,
49*4882a593Smuzhiyun .size = S32V234_PERIPH_SIZE,
50*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
51*4882a593Smuzhiyun PTE_BLOCK_NON_SHARE
52*4882a593Smuzhiyun /* TODO: Do we need these? */
53*4882a593Smuzhiyun /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */
54*4882a593Smuzhiyun }, {
55*4882a593Smuzhiyun .virt = S32V234_DRAM_BASE2,
56*4882a593Smuzhiyun .phys = S32V234_DRAM_BASE2,
57*4882a593Smuzhiyun .size = S32V234_DRAM_SIZE2,
58*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
59*4882a593Smuzhiyun PTE_BLOCK_OUTER_SHARE
60*4882a593Smuzhiyun }, {
61*4882a593Smuzhiyun /* List terminator */
62*4882a593Smuzhiyun 0,
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun struct mm_region *mem_map = s32v234_mem_map;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun * Return the number of cores on this SOC.
72*4882a593Smuzhiyun */
cpu_numcores(void)73*4882a593Smuzhiyun int cpu_numcores(void)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun int numcores;
76*4882a593Smuzhiyun u32 mask;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun mask = cpu_mask();
79*4882a593Smuzhiyun numcores = hweight32(cpu_mask());
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Verify if M4 is deactivated */
82*4882a593Smuzhiyun if (mask & 0x1)
83*4882a593Smuzhiyun numcores--;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return numcores;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #if defined(CONFIG_ARCH_EARLY_INIT_R)
arch_early_init_r(void)89*4882a593Smuzhiyun int arch_early_init_r(void)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun int rv;
92*4882a593Smuzhiyun asm volatile ("dsb sy");
93*4882a593Smuzhiyun rv = fsl_s32v234_wake_seconday_cores();
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun if (rv)
96*4882a593Smuzhiyun printf("Did not wake secondary cores\n");
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun asm volatile ("sev");
99*4882a593Smuzhiyun return 0;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun #endif /* CONFIG_ARCH_EARLY_INIT_R */
102