1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2014-2015 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <spl.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <fsl_ifc.h>
11*4882a593Smuzhiyun #include <i2c.h>
12*4882a593Smuzhiyun #include <fsl_csu.h>
13*4882a593Smuzhiyun #include <asm/arch/fdt.h>
14*4882a593Smuzhiyun #include <asm/arch/ppa.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
spl_boot_device(void)18*4882a593Smuzhiyun u32 spl_boot_device(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun #ifdef CONFIG_SPL_MMC_SUPPORT
21*4882a593Smuzhiyun return BOOT_DEVICE_MMC1;
22*4882a593Smuzhiyun #endif
23*4882a593Smuzhiyun #ifdef CONFIG_SPL_NAND_SUPPORT
24*4882a593Smuzhiyun return BOOT_DEVICE_NAND;
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun return 0;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
spl_boot_mode(const u32 boot_device)29*4882a593Smuzhiyun u32 spl_boot_mode(const u32 boot_device)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun switch (spl_boot_device()) {
32*4882a593Smuzhiyun case BOOT_DEVICE_MMC1:
33*4882a593Smuzhiyun #ifdef CONFIG_SPL_FAT_SUPPORT
34*4882a593Smuzhiyun return MMCSD_MODE_FS;
35*4882a593Smuzhiyun #else
36*4882a593Smuzhiyun return MMCSD_MODE_RAW;
37*4882a593Smuzhiyun #endif
38*4882a593Smuzhiyun case BOOT_DEVICE_NAND:
39*4882a593Smuzhiyun return 0;
40*4882a593Smuzhiyun default:
41*4882a593Smuzhiyun puts("spl: error: unsupported device\n");
42*4882a593Smuzhiyun hang();
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD
47*4882a593Smuzhiyun
spl_board_init(void)48*4882a593Smuzhiyun void spl_board_init(void)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2)
51*4882a593Smuzhiyun /*
52*4882a593Smuzhiyun * In case of Secure Boot, the IBR configures the SMMU
53*4882a593Smuzhiyun * to allow only Secure transactions.
54*4882a593Smuzhiyun * SMMU must be reset in bypass mode.
55*4882a593Smuzhiyun * Set the ClientPD bit and Clear the USFCFG Bit
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun u32 val;
58*4882a593Smuzhiyun val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
59*4882a593Smuzhiyun out_le32(SMMU_SCR0, val);
60*4882a593Smuzhiyun val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
61*4882a593Smuzhiyun out_le32(SMMU_NSCR0, val);
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
64*4882a593Smuzhiyun enable_layerscape_ns_access();
65*4882a593Smuzhiyun #endif
66*4882a593Smuzhiyun #ifdef CONFIG_SPL_FSL_LS_PPA
67*4882a593Smuzhiyun ppa_init();
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
board_init_f(ulong dummy)71*4882a593Smuzhiyun void board_init_f(ulong dummy)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun /* Clear global data */
74*4882a593Smuzhiyun memset((void *)gd, 0, sizeof(gd_t));
75*4882a593Smuzhiyun board_early_init_f();
76*4882a593Smuzhiyun timer_init();
77*4882a593Smuzhiyun #ifdef CONFIG_ARCH_LS2080A
78*4882a593Smuzhiyun env_init();
79*4882a593Smuzhiyun #endif
80*4882a593Smuzhiyun get_clocks();
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun preloader_console_init();
83*4882a593Smuzhiyun spl_set_bd();
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #ifdef CONFIG_SPL_I2C_SUPPORT
86*4882a593Smuzhiyun i2c_init_all();
87*4882a593Smuzhiyun #endif
88*4882a593Smuzhiyun dram_init();
89*4882a593Smuzhiyun #ifdef CONFIG_SPL_FSL_LS_PPA
90*4882a593Smuzhiyun #ifndef CONFIG_SYS_MEM_RESERVE_SECURE
91*4882a593Smuzhiyun #error Need secure RAM for PPA
92*4882a593Smuzhiyun #endif
93*4882a593Smuzhiyun /*
94*4882a593Smuzhiyun * Secure memory location is determined in dram_init_banksize().
95*4882a593Smuzhiyun * gd->ram_size is deducted by the size of secure ram.
96*4882a593Smuzhiyun */
97*4882a593Smuzhiyun dram_init_banksize();
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /*
100*4882a593Smuzhiyun * After dram_init_bank_size(), we know U-Boot only uses the first
101*4882a593Smuzhiyun * memory bank regardless how big the memory is.
102*4882a593Smuzhiyun */
103*4882a593Smuzhiyun gd->ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /*
106*4882a593Smuzhiyun * If PPA is loaded, U-Boot will resume running at EL2.
107*4882a593Smuzhiyun * Cache and MMU will be enabled. Need a place for TLB.
108*4882a593Smuzhiyun * U-Boot will be relocated to the end of available memory
109*4882a593Smuzhiyun * in first bank. At this point, we cannot know how much
110*4882a593Smuzhiyun * memory U-Boot uses. Put TLB table lower by SPL_TLB_SETBACK
111*4882a593Smuzhiyun * to avoid overlapping. As soon as the RAM version U-Boot sets
112*4882a593Smuzhiyun * up new MMU, this space is no longer needed.
113*4882a593Smuzhiyun */
114*4882a593Smuzhiyun gd->ram_top -= SPL_TLB_SETBACK;
115*4882a593Smuzhiyun gd->arch.tlb_size = PGTABLE_SIZE;
116*4882a593Smuzhiyun gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1);
117*4882a593Smuzhiyun gd->arch.tlb_allocated = gd->arch.tlb_addr;
118*4882a593Smuzhiyun #endif /* CONFIG_SPL_FSL_LS_PPA */
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun #endif /* CONFIG_SPL_BUILD */
121