1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/arch/fsl_serdes.h>
9*4882a593Smuzhiyun #include <asm/arch/immap_lsch2.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun struct serdes_config {
12*4882a593Smuzhiyun u32 protocol;
13*4882a593Smuzhiyun u8 lanes[SRDS_MAX_LANES];
14*4882a593Smuzhiyun };
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static struct serdes_config serdes1_cfg_tbl[] = {
17*4882a593Smuzhiyun /* SerDes 1 */
18*4882a593Smuzhiyun {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3} },
19*4882a593Smuzhiyun {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
20*4882a593Smuzhiyun {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3} },
21*4882a593Smuzhiyun {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA1} },
22*4882a593Smuzhiyun {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
23*4882a593Smuzhiyun {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
24*4882a593Smuzhiyun {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
25*4882a593Smuzhiyun PCIE3} },
26*4882a593Smuzhiyun {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
27*4882a593Smuzhiyun {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA1} },
28*4882a593Smuzhiyun {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
29*4882a593Smuzhiyun {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA1} },
30*4882a593Smuzhiyun {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1} },
31*4882a593Smuzhiyun {0x9998, {PCIE1, PCIE2, PCIE3, SATA1} },
32*4882a593Smuzhiyun {0x6058, {PCIE1, PCIE1, PCIE2, SATA1} },
33*4882a593Smuzhiyun {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3} },
34*4882a593Smuzhiyun {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3} },
35*4882a593Smuzhiyun {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3} },
36*4882a593Smuzhiyun {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
37*4882a593Smuzhiyun SGMII_FM1_DTSEC6} },
38*4882a593Smuzhiyun {}
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun static struct serdes_config *serdes_cfg_tbl[] = {
42*4882a593Smuzhiyun serdes1_cfg_tbl,
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
serdes_get_prtcl(int serdes,int cfg,int lane)45*4882a593Smuzhiyun enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct serdes_config *ptr;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
50*4882a593Smuzhiyun return 0;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun ptr = serdes_cfg_tbl[serdes];
53*4882a593Smuzhiyun while (ptr->protocol) {
54*4882a593Smuzhiyun if (ptr->protocol == cfg)
55*4882a593Smuzhiyun return ptr->lanes[lane];
56*4882a593Smuzhiyun ptr++;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
is_serdes_prtcl_valid(int serdes,u32 prtcl)62*4882a593Smuzhiyun int is_serdes_prtcl_valid(int serdes, u32 prtcl)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun int i;
65*4882a593Smuzhiyun struct serdes_config *ptr;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun ptr = serdes_cfg_tbl[serdes];
71*4882a593Smuzhiyun while (ptr->protocol) {
72*4882a593Smuzhiyun if (ptr->protocol == prtcl)
73*4882a593Smuzhiyun break;
74*4882a593Smuzhiyun ptr++;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (!ptr->protocol)
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun for (i = 0; i < SRDS_MAX_LANES; i++) {
81*4882a593Smuzhiyun if (ptr->lanes[i] != NONE)
82*4882a593Smuzhiyun return 1;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return 0;
86*4882a593Smuzhiyun }
87